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https://github.com/azahar-emu/dynarmic
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IR: Remove unused microinstructions NegateLowWord and NegateHighWord
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@ -1275,26 +1275,6 @@ void EmitX64::EmitCountLeadingZeros(IR::Block&, IR::Inst* inst) {
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}
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}
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}
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}
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void EmitX64::EmitNegateLowWord(IR::Block&, IR::Inst* inst) {
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IR::Value a = inst->GetArg(0);
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Xbyak::Reg32 result = reg_alloc.UseDefGpr(a, inst).cvt32();
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code->ror(result, 16);
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code->xor(result, 0xFFFF0000);
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code->add(result, 0x00010000);
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code->ror(result, 16);
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}
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void EmitX64::EmitNegateHighWord(IR::Block&, IR::Inst* inst) {
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IR::Value a = inst->GetArg(0);
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Xbyak::Reg32 result = reg_alloc.UseDefGpr(a, inst).cvt32();
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code->xor(result, 0xFFFF0000);
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code->add(result, 0x00010000);
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}
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void EmitX64::EmitSignedSaturatedAdd(IR::Block& block, IR::Inst* inst) {
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void EmitX64::EmitSignedSaturatedAdd(IR::Block& block, IR::Inst* inst) {
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auto overflow_inst = inst->GetAssociatedPseudoOperation(IR::Opcode::GetOverflowFromOp);
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auto overflow_inst = inst->GetAssociatedPseudoOperation(IR::Opcode::GetOverflowFromOp);
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@ -328,14 +328,6 @@ Value IREmitter::CountLeadingZeros(const Value& a) {
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return Inst(Opcode::CountLeadingZeros, {a});
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return Inst(Opcode::CountLeadingZeros, {a});
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}
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}
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Value IREmitter::NegateLowWord(const Value& a) {
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return Inst(Opcode::NegateLowWord, {a});
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}
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Value IREmitter::NegateHighWord(const Value& a) {
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return Inst(Opcode::NegateHighWord, {a});
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}
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IREmitter::ResultAndOverflow IREmitter::SignedSaturatedAdd(const Value& a, const Value& b) {
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IREmitter::ResultAndOverflow IREmitter::SignedSaturatedAdd(const Value& a, const Value& b) {
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auto result = Inst(Opcode::SignedSaturatedAdd, {a, b});
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auto result = Inst(Opcode::SignedSaturatedAdd, {a, b});
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auto overflow = Inst(Opcode::GetOverflowFromOp, {result});
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auto overflow = Inst(Opcode::GetOverflowFromOp, {result});
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@ -133,8 +133,6 @@ public:
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Value ByteReverseHalf(const Value& a);
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Value ByteReverseHalf(const Value& a);
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Value ByteReverseDual(const Value& a);
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Value ByteReverseDual(const Value& a);
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Value CountLeadingZeros(const Value& a);
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Value CountLeadingZeros(const Value& a);
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Value NegateLowWord(const Value& a);
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Value NegateHighWord(const Value& a);
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ResultAndOverflow SignedSaturatedAdd(const Value& a, const Value& b);
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ResultAndOverflow SignedSaturatedAdd(const Value& a, const Value& b);
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ResultAndOverflow SignedSaturatedSub(const Value& a, const Value& b);
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ResultAndOverflow SignedSaturatedSub(const Value& a, const Value& b);
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@ -73,8 +73,6 @@ OPCODE(ByteReverseWord, T::U32, T::U32
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OPCODE(ByteReverseHalf, T::U16, T::U16 )
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OPCODE(ByteReverseHalf, T::U16, T::U16 )
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OPCODE(ByteReverseDual, T::U64, T::U64 )
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OPCODE(ByteReverseDual, T::U64, T::U64 )
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OPCODE(CountLeadingZeros, T::U32, T::U32 )
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OPCODE(CountLeadingZeros, T::U32, T::U32 )
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OPCODE(NegateLowWord, T::U32, T::U32 )
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OPCODE(NegateHighWord, T::U32, T::U32 )
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// Saturated instructions
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// Saturated instructions
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OPCODE(SignedSaturatedAdd, T::U32, T::U32, T::U32 )
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OPCODE(SignedSaturatedAdd, T::U32, T::U32, T::U32 )
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