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translate_arm/packing: Invert conditionals where applicable

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Lioncash 2019-03-01 01:23:48 -05:00 committed by MerryMage
parent c711188f46
commit 3c00a616d6
1 changed files with 22 additions and 14 deletions
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36
src/frontend/A32/translate/translate_arm/packing.cpp
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@ -8,31 +8,39 @@
namespace Dynarmic::A32 { namespace Dynarmic::A32 {
// PKHBT<c> <Rd>, <Rn>, <Rm>{, LSL #<imm>}
bool ArmTranslatorVisitor::arm_PKHBT(Cond cond, Reg n, Reg d, Imm5 imm5, Reg m) { bool ArmTranslatorVisitor::arm_PKHBT(Cond cond, Reg n, Reg d, Imm5 imm5, Reg m) {
if (n == Reg::PC || d == Reg::PC || m == Reg::PC) if (n == Reg::PC || d == Reg::PC || m == Reg::PC) {
return UnpredictableInstruction(); return UnpredictableInstruction();
if (ConditionPassed(cond)) {
auto shifted = EmitImmShift(ir.GetRegister(m), ShiftType::LSL, imm5, ir.Imm1(false)).result;
auto lower_half = ir.And(ir.GetRegister(n), ir.Imm32(0x0000FFFF));
auto upper_half = ir.And(shifted, ir.Imm32(0xFFFF0000));
ir.SetRegister(d, ir.Or(lower_half, upper_half));
} }
if (!ConditionPassed(cond)) {
return true; return true;
} }
bool ArmTranslatorVisitor::arm_PKHTB(Cond cond, Reg n, Reg d, Imm5 imm5, Reg m) { const auto shifted = EmitImmShift(ir.GetRegister(m), ShiftType::LSL, imm5, ir.Imm1(false)).result;
if (n == Reg::PC || d == Reg::PC || m == Reg::PC) const auto lower_half = ir.And(ir.GetRegister(n), ir.Imm32(0x0000FFFF));
return UnpredictableInstruction(); const auto upper_half = ir.And(shifted, ir.Imm32(0xFFFF0000));
if (ConditionPassed(cond)) {
auto shifted = EmitImmShift(ir.GetRegister(m), ShiftType::ASR, imm5, ir.Imm1(false)).result;
auto lower_half = ir.And(shifted, ir.Imm32(0x0000FFFF));
auto upper_half = ir.And(ir.GetRegister(n), ir.Imm32(0xFFFF0000));
ir.SetRegister(d, ir.Or(lower_half, upper_half)); ir.SetRegister(d, ir.Or(lower_half, upper_half));
return true;
} }
// PKHTB<c> <Rd>, <Rn>, <Rm>{, ASR #<imm>}
bool ArmTranslatorVisitor::arm_PKHTB(Cond cond, Reg n, Reg d, Imm5 imm5, Reg m) {
if (n == Reg::PC || d == Reg::PC || m == Reg::PC) {
return UnpredictableInstruction();
}
if (!ConditionPassed(cond)) {
return true;
}
const auto shifted = EmitImmShift(ir.GetRegister(m), ShiftType::ASR, imm5, ir.Imm1(false)).result;
const auto lower_half = ir.And(shifted, ir.Imm32(0x0000FFFF));
const auto upper_half = ir.And(ir.GetRegister(n), ir.Imm32(0xFFFF0000));
ir.SetRegister(d, ir.Or(lower_half, upper_half));
return true; return true;
} }