diff --git a/src/frontend/A32/decoder/thumb32.inc b/src/frontend/A32/decoder/thumb32.inc index bf2bc56a..53a148d4 100644 --- a/src/frontend/A32/decoder/thumb32.inc +++ b/src/frontend/A32/decoder/thumb32.inc @@ -124,20 +124,20 @@ INST(thumb32_UDF, "Invalid decoding", "11110-111-------10-0-- INST(thumb32_B_cond, "B (cond)", "11110Sccccvvvvvv10i0ivvvvvvvvvvv") // Store Single Data Item -//INST(thumb32_STRB_imm_1, "STRB (imm)", "111110000000--------1--1--------") -//INST(thumb32_STRB_imm_2, "STRB (imm)", "111110000000--------1100--------") -//INST(thumb32_STRB_imm_3, "STRB (imm)", "111110001000--------------------") -//INST(thumb32_STRBT, "STRBT", "111110000000--------1110--------") +INST(thumb32_STRB_imm_1, "STRB (imm)", "111110000000nnnntttt1PU1iiiiiiii") +INST(thumb32_STRB_imm_2, "STRB (imm)", "111110000000nnnntttt1100iiiiiiii") +INST(thumb32_STRB_imm_3, "STRB (imm)", "111110001000nnnnttttiiiiiiiiiiii") +INST(thumb32_STRBT, "STRBT", "111110000000nnnntttt1110iiiiiiii") INST(thumb32_STRB, "STRB (reg)", "111110000000nnnntttt000000iimmmm") -//INST(thumb32_STRH_imm_1, "STRH (imm)", "111110000010--------1--1--------") -//INST(thumb32_STRH_imm_2, "STRH (imm)", "111110000010--------1100--------") -//INST(thumb32_STRH_imm_3, "STRH (imm)", "111110001010--------------------") -//INST(thumb32_STRHT, "STRHT", "111110000010--------1110--------") +INST(thumb32_STRH_imm_1, "STRH (imm)", "111110000010nnnntttt1PU1iiiiiiii") +INST(thumb32_STRH_imm_2, "STRH (imm)", "111110000010nnnntttt1100iiiiiiii") +INST(thumb32_STRH_imm_3, "STRH (imm)", "111110001010nnnnttttiiiiiiiiiiii") +INST(thumb32_STRHT, "STRHT", "111110000010nnnntttt1110iiiiiiii") INST(thumb32_STRH, "STRH (reg)", "111110000010nnnntttt000000iimmmm") -//INST(thumb32_STR_imm_1, "STR (imm)", "111110000100--------1--1--------") -//INST(thumb32_STR_imm_2, "STR (imm)", "111110000100--------1100--------") -//INST(thumb32_STR_imm_3, "STR (imm)", "111110001100--------------------") -//INST(thumb32_STRT, "STRT", "111110000100--------1110--------") +INST(thumb32_STR_imm_1, "STR (imm)", "111110000100nnnntttt1PU1iiiiiiii") +INST(thumb32_STR_imm_2, "STR (imm)", "111110000100nnnntttt1100iiiiiiii") +INST(thumb32_STR_imm_3, "STR (imm)", "111110001100nnnnttttiiiiiiiiiiii") +INST(thumb32_STRT, "STRT", "111110000100nnnntttt1110iiiiiiii") INST(thumb32_STR_reg, "STR (reg)", "111110000100nnnntttt000000iimmmm") // Load Byte and Memory Hints diff --git a/src/frontend/A32/translate/impl/thumb32_store_single_data_item.cpp b/src/frontend/A32/translate/impl/thumb32_store_single_data_item.cpp index 0b776e75..78c56fc6 100644 --- a/src/frontend/A32/translate/impl/thumb32_store_single_data_item.cpp +++ b/src/frontend/A32/translate/impl/thumb32_store_single_data_item.cpp @@ -29,18 +29,192 @@ static bool StoreRegister(ThumbTranslatorVisitor& v, Reg n, Reg t, Imm<2> imm2, return true; } +using StoreImmFn = void (*)(ThumbTranslatorVisitor&, const IR::U32&, const IR::U32&); + +static void StoreImmByteFn(ThumbTranslatorVisitor& v, const IR::U32& address, const IR::U32& data) { + v.ir.WriteMemory8(address, v.ir.LeastSignificantByte(data)); +} + +static void StoreImmHalfFn(ThumbTranslatorVisitor& v, const IR::U32& address, const IR::U32& data) { + v.ir.WriteMemory16(address, v.ir.LeastSignificantHalf(data)); +} + +static void StoreImmWordFn(ThumbTranslatorVisitor& v, const IR::U32& address, const IR::U32& data) { + v.ir.WriteMemory32(address, data); +} + +static bool StoreImmediate(ThumbTranslatorVisitor& v, Reg n, Reg t, bool P, bool U, bool W, Imm<12> imm12, + StoreImmFn store_fn) { + const auto imm32 = imm12.ZeroExtend(); + const auto reg_n = v.ir.GetRegister(n); + const auto reg_t = v.ir.GetRegister(t); + + const IR::U32 offset_address = U ? v.ir.Add(reg_n, v.ir.Imm32(imm32)) + : v.ir.Sub(reg_n, v.ir.Imm32(imm32)); + const IR::U32 address = P ? offset_address + : reg_n; + + store_fn(v, address, reg_t); + if (W) { + v.ir.SetRegister(n, offset_address); + } + + return true; +} + +bool ThumbTranslatorVisitor::thumb32_STRB_imm_1(Reg n, Reg t, bool P, bool U, Imm<8> imm8) { + if (n == Reg::PC) { + return UndefinedInstruction(); + } + if (t == Reg::PC || n == t) { + return UnpredictableInstruction(); + } + return StoreImmediate(*this, n, t, P, U, true, Imm<12>{imm8.ZeroExtend()}, StoreImmByteFn); +} + +bool ThumbTranslatorVisitor::thumb32_STRB_imm_2(Reg n, Reg t, Imm<8> imm8) { + if (n == Reg::PC) { + return UndefinedInstruction(); + } + if (t == Reg::PC) { + return UnpredictableInstruction(); + } + return StoreImmediate(*this, n, t, true, false, false, Imm<12>{imm8.ZeroExtend()}, StoreImmByteFn); +} + +bool ThumbTranslatorVisitor::thumb32_STRB_imm_3(Reg n, Reg t, Imm<12> imm12) { + if (n == Reg::PC) { + return UndefinedInstruction(); + } + if (t == Reg::PC) { + return UnpredictableInstruction(); + } + return StoreImmediate(*this, n, t, true, true, false, imm12, StoreImmByteFn); +} + +bool ThumbTranslatorVisitor::thumb32_STRBT(Reg n, Reg t, Imm<8> imm8) { + // TODO: Add an unpredictable instruction path if this + // is executed in hypervisor mode if we ever support + // privileged execution levels. + + if (n == Reg::PC) { + return UndefinedInstruction(); + } + if (t == Reg::PC) { + return UnpredictableInstruction(); + } + + // Treat this as a normal STRB, given we don't support + // execution levels other than EL0 currently. + return StoreImmediate(*this, n, t, true, true, false, Imm<12>{imm8.ZeroExtend()}, StoreImmByteFn); +} + bool ThumbTranslatorVisitor::thumb32_STRB(Reg n, Reg t, Imm<2> imm2, Reg m) { return StoreRegister(*this, n, t, imm2, m, [this](const IR::U32& offset_address, const IR::U32& data) { ir.WriteMemory8(offset_address, ir.LeastSignificantByte(data)); }); } +bool ThumbTranslatorVisitor::thumb32_STRH_imm_1(Reg n, Reg t, bool P, bool U, Imm<8> imm8) { + if (n == Reg::PC) { + return UndefinedInstruction(); + } + if (t == Reg::PC || n == t) { + return UnpredictableInstruction(); + } + return StoreImmediate(*this, n, t, P, U, true, Imm<12>{imm8.ZeroExtend()}, StoreImmHalfFn); +} + +bool ThumbTranslatorVisitor::thumb32_STRH_imm_2(Reg n, Reg t, Imm<8> imm8) { + if (n == Reg::PC) { + return UndefinedInstruction(); + } + if (t == Reg::PC) { + return UnpredictableInstruction(); + } + return StoreImmediate(*this, n, t, true, false, false, Imm<12>{imm8.ZeroExtend()}, StoreImmHalfFn); +} + +bool ThumbTranslatorVisitor::thumb32_STRH_imm_3(Reg n, Reg t, Imm<12> imm12) { + if (n == Reg::PC) { + return UndefinedInstruction(); + } + if (t == Reg::PC) { + return UnpredictableInstruction(); + } + return StoreImmediate(*this, n, t, true, true, false, imm12, StoreImmHalfFn); +} + +bool ThumbTranslatorVisitor::thumb32_STRHT(Reg n, Reg t, Imm<8> imm8) { + // TODO: Add an unpredictable instruction path if this + // is executed in hypervisor mode if we ever support + // privileged execution levels. + + if (n == Reg::PC) { + return UndefinedInstruction(); + } + if (t == Reg::PC) { + return UnpredictableInstruction(); + } + + // Treat this as a normal STRH, given we don't support + // execution levels other than EL0 currently. + return StoreImmediate(*this, n, t, true, true, false, Imm<12>{imm8.ZeroExtend()}, StoreImmHalfFn); +} + bool ThumbTranslatorVisitor::thumb32_STRH(Reg n, Reg t, Imm<2> imm2, Reg m) { return StoreRegister(*this, n, t, imm2, m, [this](const IR::U32& offset_address, const IR::U32& data) { ir.WriteMemory16(offset_address, ir.LeastSignificantHalf(data)); }); } +bool ThumbTranslatorVisitor::thumb32_STR_imm_1(Reg n, Reg t, bool P, bool U, Imm<8> imm8) { + if (n == Reg::PC) { + return UndefinedInstruction(); + } + if (t == Reg::PC || n == t) { + return UnpredictableInstruction(); + } + return StoreImmediate(*this, n, t, P, U, true, Imm<12>{imm8.ZeroExtend()}, StoreImmWordFn); +} + +bool ThumbTranslatorVisitor::thumb32_STR_imm_2(Reg n, Reg t, Imm<8> imm8) { + if (n == Reg::PC) { + return UndefinedInstruction(); + } + if (t == Reg::PC) { + return UnpredictableInstruction(); + } + return StoreImmediate(*this, n, t, true, false, false, Imm<12>{imm8.ZeroExtend()}, StoreImmWordFn); +} + +bool ThumbTranslatorVisitor::thumb32_STR_imm_3(Reg n, Reg t, Imm<12> imm12) { + if (n == Reg::PC) { + return UndefinedInstruction(); + } + if (t == Reg::PC) { + return UnpredictableInstruction(); + } + return StoreImmediate(*this, n, t, true, true, false, imm12, StoreImmWordFn); +} + +bool ThumbTranslatorVisitor::thumb32_STRT(Reg n, Reg t, Imm<8> imm8) { + // TODO: Add an unpredictable instruction path if this + // is executed in hypervisor mode if we ever support + // privileged execution levels. + + if (n == Reg::PC) { + return UndefinedInstruction(); + } + if (t == Reg::PC) { + return UnpredictableInstruction(); + } + + // Treat this as a normal STR, given we don't support + // execution levels other than EL0 currently. + return StoreImmediate(*this, n, t, true, true, false, Imm<12>{imm8.ZeroExtend()}, StoreImmWordFn); +} + bool ThumbTranslatorVisitor::thumb32_STR_reg(Reg n, Reg t, Imm<2> imm2, Reg m) { return StoreRegister(*this, n, t, imm2, m, [this](const IR::U32& offset_address, const IR::U32& data) { ir.WriteMemory32(offset_address, data); diff --git a/src/frontend/A32/translate/impl/translate_thumb.h b/src/frontend/A32/translate/impl/translate_thumb.h index d85942fd..723a552e 100644 --- a/src/frontend/A32/translate/impl/translate_thumb.h +++ b/src/frontend/A32/translate/impl/translate_thumb.h @@ -243,8 +243,20 @@ struct ThumbTranslatorVisitor final { bool thumb32_B_cond(Imm<1> S, Cond cond, Imm<6> hi, Imm<1> j1, Imm<1> j2, Imm<11> lo); // thumb32 store single data item instructions + bool thumb32_STRB_imm_1(Reg n, Reg t, bool P, bool U, Imm<8> imm8); + bool thumb32_STRB_imm_2(Reg n, Reg t, Imm<8> imm8); + bool thumb32_STRB_imm_3(Reg n, Reg t, Imm<12> imm12); + bool thumb32_STRBT(Reg n, Reg t, Imm<8> imm8); bool thumb32_STRB(Reg n, Reg t, Imm<2> imm2, Reg m); + bool thumb32_STRH_imm_1(Reg n, Reg t, bool P, bool U, Imm<8> imm8); + bool thumb32_STRH_imm_2(Reg n, Reg t, Imm<8> imm8); + bool thumb32_STRH_imm_3(Reg n, Reg t, Imm<12> imm12); + bool thumb32_STRHT(Reg n, Reg t, Imm<8> imm8); bool thumb32_STRH(Reg n, Reg t, Imm<2> imm2, Reg m); + bool thumb32_STR_imm_1(Reg n, Reg t, bool P, bool U, Imm<8> imm8); + bool thumb32_STR_imm_2(Reg n, Reg t, Imm<8> imm8); + bool thumb32_STR_imm_3(Reg n, Reg t, Imm<12> imm12); + bool thumb32_STRT(Reg n, Reg t, Imm<8> imm8); bool thumb32_STR_reg(Reg n, Reg t, Imm<2> imm2, Reg m); // thumb32 load byte and memory hints