diff --git a/include/dynarmic/A64/config.h b/include/dynarmic/A64/config.h
index 2511b65b..9846f70a 100644
--- a/include/dynarmic/A64/config.h
+++ b/include/dynarmic/A64/config.h
@@ -69,8 +69,12 @@ enum class DataCacheOperation {
 };
 
 enum class InstructionCacheOperation {
-    // IC IVAU
+    /// IC IVAU
     InvalidateByVAToPoU,
+    /// IC IALLU
+    InvalidateAllToPoU,
+    /// IC IALLUIS
+    InvalidateAllToPoUInnerSharable
 };
 
 struct UserCallbacks {
diff --git a/src/frontend/A64/translate/impl/sys_ic.cpp b/src/frontend/A64/translate/impl/sys_ic.cpp
index d2f557f5..de54121e 100644
--- a/src/frontend/A64/translate/impl/sys_ic.cpp
+++ b/src/frontend/A64/translate/impl/sys_ic.cpp
@@ -7,21 +7,19 @@
 
 namespace Dynarmic::A64 {
 
-static bool InstructionCacheInstruction(TranslatorVisitor& v, InstructionCacheOperation op, const Reg Rt) {
-    v.ir.InstructionCacheOperationRaised(op, v.X(64, Rt));
+bool TranslatorVisitor::IC_IALLU() {
+    ir.InstructionCacheOperationRaised(InstructionCacheOperation::InvalidateAllToPoU, ir.Imm64(0));
     return true;
 }
 
-bool TranslatorVisitor::IC_IALLU() {
-    return false;
-}
-
 bool TranslatorVisitor::IC_IALLUIS() {
-    return false;
+    ir.InstructionCacheOperationRaised(InstructionCacheOperation::InvalidateAllToPoUInnerSharable, ir.Imm64(0));
+    return true;
 }
 
 bool TranslatorVisitor::IC_IVAU(Reg Rt) {
-    return InstructionCacheInstruction(*this, InstructionCacheOperation::InvalidateByVAToPoU, Rt);
+    ir.InstructionCacheOperationRaised(InstructionCacheOperation::InvalidateByVAToPoU, X(64, Rt));
+    return true;
 }
 
 } // namespace Dynarmic::A64
diff --git a/src/frontend/ir/microinstruction.cpp b/src/frontend/ir/microinstruction.cpp
index 3658aa74..f1f381df 100644
--- a/src/frontend/ir/microinstruction.cpp
+++ b/src/frontend/ir/microinstruction.cpp
@@ -520,18 +520,19 @@ bool Inst::IsSetCheckBitOperation() const {
 }
 
 bool Inst::MayHaveSideEffects() const {
-    return op == Opcode::PushRSB                        ||
-           op == Opcode::A64DataCacheOperationRaised    ||
-           IsSetCheckBitOperation()                     ||
-           IsBarrier()                                  ||
-           CausesCPUException()                         ||
-           WritesToCoreRegister()                       ||
-           WritesToSystemRegister()                     ||
-           WritesToCPSR()                               ||
-           WritesToFPCR()                               ||
-           WritesToFPSR()                               ||
-           AltersExclusiveState()                       ||
-           IsMemoryWrite()                              ||
+    return op == Opcode::PushRSB                            ||
+           op == Opcode::A64DataCacheOperationRaised        ||
+           op == Opcode::A64InstructionCacheOperationRaised ||
+           IsSetCheckBitOperation()                         ||
+           IsBarrier()                                      ||
+           CausesCPUException()                             ||
+           WritesToCoreRegister()                           ||
+           WritesToSystemRegister()                         ||
+           WritesToCPSR()                                   ||
+           WritesToFPCR()                                   ||
+           WritesToFPSR()                                   ||
+           AltersExclusiveState()                           ||
+           IsMemoryWrite()                                  ||
            IsCoprocessorInstruction();
 }
 
diff --git a/tests/A64/a64.cpp b/tests/A64/a64.cpp
index 5db20ebe..1cdb7628 100644
--- a/tests/A64/a64.cpp
+++ b/tests/A64/a64.cpp
@@ -634,20 +634,3 @@ TEST_CASE("A64: Optimization failure when folding ADD", "[a64]") {
     REQUIRE(jit.GetPstate() == 0x20000000);
     REQUIRE(jit.GetVector(30) == Vector{0xf7f6f5f4, 0});
 }
-
-TEST_CASE("A64: IC", "[a64]") {
-    A64TestEnv env;
-    A64::Jit jit{A64::UserConfig{&env}};
-
-    env.code_mem.emplace_back(0xd50b7520); // ic ivau, x0
-    env.code_mem.emplace_back(0x14000000); // B .
-
-    jit.SetRegister(0, 0);
-    jit.SetPC(0);
-
-    env.ticks_left = 2;
-    jit.Run();
-
-    REQUIRE(jit.GetRegister(0) == 0);
-    REQUIRE(jit.GetPC() == 4);
-}