14 Commits

Author	SHA1	Message	Date
bunnei	218980cf69	load_store: Implement LDRSB and LDRSH.	2016-08-11 17:18:20 +01:00
MerryMage	d0d51ba346	TranslateArm: Implement STM, STMDA, STMDB, STMIB	2016-08-08 22:49:11 +01:00
MerryMage	85549d7ae2	TranslateArm: Implement LDM, LDMDA, LDMDB, LDMIB	2016-08-08 22:26:06 +01:00
MerryMage	7915f97d98	TranslateArm/LoadStore: Add default case to switches for arm_LDRD_imm and arm_LDRD_reg (fixes GCC warning)	2016-08-06 20:42:06 +01:00
bunnei	2448d52394	load_store: Use correct types for LDR/STR.	2016-08-05 20:51:32 -04:00
bunnei	8c2300d477	arm: Implement LDRD reg/imm instructions.	2016-08-05 20:05:02 -04:00
bunnei	ec3a98cf95	arm: Implement LDRH reg/imm instructions.	2016-08-05 20:05:01 -04:00
bunnei	192a0fba7a	arm: Implement LDRB reg/imm instructions.	2016-08-05 20:05:00 -04:00
bunnei	dfb318f208	arm: Implement STRD reg/imm instructions.	2016-08-05 20:04:59 -04:00
bunnei	e931dc2496	arm: Implement STRH reg/imm instructions.	2016-08-05 20:04:58 -04:00
bunnei	9f77662b24	arm: Implement STRB reg/imm instructions.	2016-08-05 20:04:57 -04:00
bunnei	caab1bbc7c	arm: Implement STR reg/imm instructions.	2016-08-05 20:04:56 -04:00
bunnei	b09ecb4532	arm: Implement LDR reg/imm instructions.	2016-08-05 20:04:55 -04:00
MerryMage	a875c0c720	TranslateArm: Stub more ARM instructions	2016-08-02 21:59:33 +01:00