Lioncash
224ff0afaa
A64: Implement SQRDMULH's by-index vector variant
2020-04-22 20:58:11 +01:00
Lioncash
3a3542414b
A64: Implement FRECPX's half-precision floating point variant
2020-04-22 20:58:11 +01:00
Lioncash
126c29a9e9
A64: Implement SQSHRN, SQSHRUN, and UQSHRN's scalar variants
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These can just be implemented in terms of the vector variants for the
time being.
2020-04-22 20:58:11 +01:00
Merry
bbd5330ad2
Merge pull request #447 from lioncash/flag
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A64: Implement CFINV, RMIF, AXFlag and XAFlag
2020-04-22 20:58:11 +01:00
Merry
fb039e232c
Merge pull request #442 from lioncash/fcvtxn
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A64: Implement scalar and vector variants of FCVTXN
2020-04-22 20:58:11 +01:00
Merry
4f937c1ee1
Merge pull request #446 from lioncash/sqshl
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A64: Implement scalar variants of SQSHL (register) and UQSHL (register)
2020-04-22 20:58:11 +01:00
Lioncash
aa22db534b
A64: Implement AXFlag and XAFlag
2020-04-22 20:58:11 +01:00
Merry
d74cccbc84
Merge pull request #445 from lioncash/sqrt
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A64: Implement single and double-precision vector variant of FSQRT
2020-04-22 20:58:11 +01:00
Lioncash
20ffe568d0
A64: Implement RMIF
2020-04-22 20:58:11 +01:00
Lioncash
51b526e453
A64: Implement CFINV
2020-04-22 20:58:11 +01:00
Lioncash
d3515279df
A64: Implement the vector version of FCVTXN
2020-04-22 20:58:10 +01:00
Lioncash
17aea0b997
A64: Implement UQSHL (register)'s scalar variant
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This can be implemented in terms of the vector variant.
2020-04-22 20:58:10 +01:00
Lioncash
c99d4b762e
A64: Implement single and double-precision vector variant of FSQRT
2020-04-22 20:58:10 +01:00
Lioncash
54e0b487f3
A64: Rearrange flag format/manipulation instructions
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Gives these instructions better categorical labeling.
2020-04-22 20:58:10 +01:00
Lioncash
4339a8fff6
A64: Implement the scalar version of FCVTXN
2020-04-22 20:58:10 +01:00
Lioncash
35ddf68ad5
A64: Implement SQSHL (register)'s scalar variant
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We can implement this in terms of the vector variant.
2020-04-22 20:58:10 +01:00
Merry
40b081438a
Merge pull request #439 from lioncash/fcmla
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A64: Implement FCADD and FCMLA
2020-04-22 20:58:10 +01:00
Merry
d91192681a
Merge pull request #438 from lioncash/fmulx
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A64: Implement scalar double/single precision FMULX (by element)
2020-04-22 20:58:10 +01:00
Lioncash
ed29ef8cca
A64: Implement FCMLA
2020-04-22 20:58:10 +01:00
Merry
9f11720a69
Merge pull request #437 from lioncash/frecpx
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A64: Implement FRECPX (single, double precision)
2020-04-22 20:58:10 +01:00
Lioncash
bdcea0b0dc
A64: Implement scalar double/single precision FMULX (by element)
2020-04-22 20:58:10 +01:00
Lioncash
5ce17574f9
A64: Implement FCADD
2020-04-22 20:58:10 +01:00
Lioncash
e44730ba6d
A64: Implement FRECPX (single, double precision)
2020-04-22 20:58:10 +01:00
Lioncash
bfaeb08d3c
A64: Implement LDNP/STNP
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LDNP and STNP indicate that a memory access is non-temporal/streaming
(i.e. unlikely to be repeated), allowing data caching to not be
performed. However, given this is only a hint, we can treat these two
instructions as regular LDP and STP instructions for the time being.
2020-04-22 20:58:10 +01:00
MerryMage
e3898e628e
A64: Implement FMULX (by element), single and double precision variants
2020-04-22 20:57:37 +01:00
MerryMage
c106d8cedf
A64: Implement FMULX, vector single-precision and double-precision variant
2020-04-22 20:57:37 +01:00
V.Kalyuzhny
764a93bf5a
Switch boost::optional to std::optional
2020-04-22 20:57:37 +01:00
Lioncash
f1a66c37ba
a64: Add ARMv8.4+ instructions encodings to the encoding table
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Keeps the table up to date with the ARM specification.
2020-04-22 20:57:37 +01:00
MerryMage
09bf273bc8
A64: Implement SCVTF, UCVTF (vector, fixed-point), scalar variant
2020-04-22 20:55:06 +01:00
MerryMage
f9129db6fd
A64: Implement FCVTZS, FCVTZU, UCVTF, SCVTF (vector, fixed-point), vector variant
2020-04-22 20:55:06 +01:00
Lioncash
48df9b9a7d
A64: Implement UQSHL's vector immediate and register variants
2020-04-22 20:55:06 +01:00
Lioncash
6b5ea6ee66
A64: Implement BRK
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Currently, we can just implement this as part of the exception
interface, similar to how it's done for the A32 interface with BKPT.
2020-04-22 20:55:06 +01:00
MerryMage
027b0ef725
A64: Implement SCVTF, UCVTF (scalar, fixed-point)
2020-04-22 20:55:06 +01:00
Lioncash
616a153c16
A64: Implement SQSHL's vector immediate variant
2020-04-22 20:55:06 +01:00
Lioncash
e8b0f25dff
A64: Implement SQSHL's vector register variant
2020-04-22 20:55:06 +01:00
Lioncash
2e0fcd6161
A64: Implement CLS's vector variant
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Leverages CLZ like the integral variant does.
2020-04-22 20:55:06 +01:00
MerryMage
12243692f5
A64: Implement SQRDMULH (vector), vector variant
2020-04-22 20:55:06 +01:00
MerryMage
a9ffcf08b1
A64: Implement SQDMULL (vector), vector variant
2020-04-22 20:55:06 +01:00
Lioncash
112cff9ab9
A64: Implement CLZ's vector variant
2020-04-22 20:55:06 +01:00
Lioncash
14e026a7f0
A64: Implement USQADD's scalar and vector variants
2020-04-22 20:55:05 +01:00
Lioncash
18ad7f237d
A64: Implement SUQADD's scalar and vector variants
2020-04-22 20:55:05 +01:00
Lioncash
9a3d38d2ee
A64: Implement SMLAL{2}, SMLSL{2}, UMLAL{2}, and UMLSL{2}'s vector by-element variants
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We can simply modify the general function made for SMULL{2} and
UMULL{2}'s by-element variants to also handle the other multiply-based
by-element variants.
2020-04-22 20:55:05 +01:00
Lioncash
6ccfbc9b39
A64: Implement UMULL{2}'s vector by-element variant
2020-04-22 20:55:05 +01:00
Lioncash
58e21f175c
A64: Implement SMULL{2}'s vector by-element variant
2020-04-22 20:55:05 +01:00
Lioncash
0a3976059f
A64: Implement URSQRTE
2020-04-22 20:55:05 +01:00
Lioncash
bd3582e811
A64: Implement URECPE
2020-04-22 20:55:05 +01:00
Lioncash
740ffa52ae
A64: Implement SQNEG's scalar and vector variant
2020-04-22 20:53:46 +01:00
Lioncash
f5fb496e7e
A64: Implement SQDMULH's by-element scalar variant
2020-04-22 20:53:46 +01:00
Lioncash
40f0576995
A64: Implement SQDMULH's by-element vector variant
2020-04-22 20:53:46 +01:00
Lioncash
1a69a61cb4
A64: Implement SQDMULH's scalar variant
2020-04-22 20:53:46 +01:00
