70 Commits

Author	SHA1	Message	Date
Lioncash	93ed3441b7	A32: Implement ASIMD VCLS/VCLZ/VCNT	2020-06-16 09:54:28 +01:00
Lioncash	15b3de95e4	A32: Implement VNEG	2020-06-16 01:53:21 +01:00
MerryMage	f3845cea9a	A32: Implement ASIMD VQSUB instruction	2020-05-30 18:19:17 +01:00
MerryMage	16ff880f8f	A32: Implement ASIMD VQADD	2020-05-30 16:09:37 +01:00
MerryMage	3a50d444dc	A32: Implement ASIMD VHSUB	2020-05-28 22:29:00 +01:00
MerryMage	205e6c5a56	A32: Implement ASIMD VRHADD	2020-05-28 22:29:00 +01:00
MerryMage	946eb03a3b	A32: Implement ASIMD VHADD	2020-05-28 22:29:00 +01:00
Lioncash	fc112e61f2	A32: Implement ASIMD modified immediate functions ... Implements VBIC, VMOV, VMVN, and VORR modified immediate instructions.	2020-05-24 23:55:47 +01:00
Lioncash	659d78c9c4	A32: Implement ASIMD VSWP ... A trivial one to implement, this just swaps the contents of two registers in place.	2020-05-22 19:43:24 +01:00
MerryMage	d0b45f6150	A32: Implement ARMv8 VST{1-4} (multiple)	2020-05-17 17:01:39 +01:00
Lioncash	f42b3ad4a0	A32: Implement ASIMD VBIF (register)	2020-05-16 20:22:12 +01:00
Lioncash	ee9a81dcba	A32: Implement ASIMD VBIT (register)	2020-05-16 20:22:12 +01:00
Lioncash	d624059ead	A32: Implement ASIMD VBSL (register)	2020-05-16 20:22:12 +01:00
Lioncash	4b5e3437cf	A32: Implement ASIMD VEOR (register)	2020-05-16 20:22:12 +01:00
Lioncash	67b284f6fa	A32: Implement ASIMD VORN (register)	2020-05-16 20:22:12 +01:00
Lioncash	1fdd90ca2a	A32: Implement ASIMD VORR (register)	2020-05-16 20:22:12 +01:00
Lioncash	64fa804dd4	A32: Implement ASIMD VBIC (register)	2020-05-16 20:22:12 +01:00
Lioncash	0441ab81a1	A32: Implement ASIMD VAND (register)	2020-05-16 20:22:12 +01:00
MerryMage	1a0bc5ba91	A32/ASIMD: ARMv8: Implement VLD{1-4} (multiple)	2020-05-16 14:11:23 +01:00
MerryMage	9a38c7324f	A32: Add decoders for remaining v7 instructions	2020-05-10 10:50:34 +01:00