MerryMage
28f27bc19d
A32: Implement ASIMD VEXT
2020-06-20 19:05:14 +01:00
MerryMage
15ee562dd0
decoder/asimd: Add misc data-processing instructions
2020-06-20 15:39:00 +01:00
MerryMage
92cb4a5a34
A32: Implement ASIMD VRSQRTE
2020-06-20 15:13:22 +01:00
MerryMage
6f59c2cd8e
A32: Implement ASIMD VRECPE
2020-06-20 15:07:06 +01:00
MerryMage
d3dc50d718
A32: Implement ASIMD VRSQRTS
2020-06-20 15:06:06 +01:00
MerryMage
8f506c80c3
A32: Implement ASIMD VRECPS
2020-06-20 14:39:05 +01:00
MerryMage
9eef4f7471
A32: Implement ASIMD VMLA, VMLS (floating-point)
2020-06-20 14:31:06 +01:00
MerryMage
60f6e729ac
A32: Implement ASIMD VABD (floating-point)
2020-06-20 14:25:04 +01:00
MerryMage
f58e247ef3
A32: Implement ASIMD VPADD (floating-point)
2020-06-20 14:25:04 +01:00
MerryMage
e006f0a205
A32: Implement ASIMD VSUB (floating-point)
2020-06-20 14:20:28 +01:00
MerryMage
4c939b9d0a
A32: Implement ASIMD VADD (floating-point)
2020-06-20 14:20:28 +01:00
MerryMage
5ec8e48593
A32: Implement ASIMD VMUL (floating-point)
...
* Also add fpcr_controlled arguments to FPVectorMul IR instruction
* Merge ASIMD floating-point instruction implementations
2020-06-20 14:20:28 +01:00
MerryMage
bb4f3aa407
A32: Implement ASIMD VMAX, VMIN (floating-point)
2020-06-20 03:21:07 +01:00
Lioncash
8d067d5d60
A32: Implement ASIMD VMUL (integer and polynomial)
2020-06-20 00:53:56 +01:00
Lioncash
ed6ca58058
A32: Implement ASIMD VCEQ, VCGE, VCGT, VCLE, VCLT with zero
...
Fairly self-explanatory, we can leverage the existing IR functions for
the purpose of these instructions.
In the integer case, we can just insert function pointers
into an array and index it, given all comparison primitives exist
already for the integer side of things.
2020-06-20 00:50:40 +01:00
Lioncash
794440cf8d
A32: Implement ASIMD VRSHL
2020-06-19 21:27:48 +01:00
Lioncash
682621ef1a
A32: Implement ASIMD VQSHL (register)
2020-06-19 21:27:48 +01:00
Lioncash
e46fb98cc5
A32: Implement ASIMD VSHL (register)
2020-06-19 21:27:48 +01:00
Lioncash
551e207661
A32: Implement ASIMD VSUB (integer)
2020-06-19 11:31:38 +01:00
Lioncash
4d6f68525d
A32: Implement ASIMD VADD (integer)
2020-06-19 11:31:38 +01:00
Lioncash
fbdae61c13
A32: Implement ASIMD VMVN (register)
...
Fairly straightforward
2020-06-19 11:31:14 +01:00
merry
687c604197
Merge pull request #532 from lioncash/shift
...
A32: Implement several ASIMD shift instructions
2020-06-19 00:22:18 +01:00
MerryMage
d34763242c
Revert "A32: Implement ASIMD VCEQ, VCGE, VCGT, VCLE, VCLT with zero"
...
This reverts commit 179951b10f6f7eb7b608574703ec8fe46bf5f63f.
These instructions require StandardFPSCRValue.
2020-06-18 17:38:40 +01:00
Lioncash
179951b10f
A32: Implement ASIMD VCEQ, VCGE, VCGT, VCLE, VCLT with zero
...
Fairly self-explanatory, we can leverage the existing IR functions for
the purpose of these instructions.
In the integer case, we can just insert function pointers
into an array and index it, given all comparison primitives exist
already for the integer side of things.
2020-06-18 17:01:57 +01:00
Lioncash
6ca20c2fe3
A32: Implement ASIMD VSLI
2020-06-18 11:51:08 -04:00
Lioncash
887732d8a8
A32: Implement ASIMD VSRI
2020-06-18 11:28:12 -04:00
Lioncash
8b98c91ecc
A32: Implement ASIMD VSHL
2020-06-18 11:18:33 -04:00
Lioncash
69c999bc66
A32: Implement ASIMD VRSRA
...
Now that we have the accumulation and rounding code in place, VRSRA is
extremely trivial to implement.
2020-06-18 11:03:39 -04:00
Lioncash
14fdd15199
A32: Implement ASIMD VRSHR
2020-06-18 11:00:45 -04:00
Lioncash
276e0b71dc
A32: Implement ASIMD VSRA
2020-06-18 11:00:27 -04:00
Lioncash
054dff7cd5
A32: Implement ASIMD VTST
2020-06-18 15:34:05 +01:00
Lioncash
6c142bc5cc
A32: Implement ASIMD VSHR
2020-06-18 10:30:20 -04:00
Lioncash
08350d06f1
A32: Implement ASIMD VQNEG
2020-06-18 09:49:29 +01:00
Lioncash
f6b665f5a4
A32: Implement ASIMD VQABS
2020-06-18 09:49:29 +01:00
Lioncash
4b371c0445
A32: Implement ASIMD VREV{16, 32, 64}
2020-06-17 10:21:59 +01:00
Lioncash
6dd2c94095
A32: Implement ASIMD VABS
...
Very similar to VNEG in that the only thing that differs is the function
called.
2020-06-16 22:42:18 +01:00
Lioncash
93ed3441b7
A32: Implement ASIMD VCLS/VCLZ/VCNT
2020-06-16 09:54:28 +01:00
Lioncash
15b3de95e4
A32: Implement VNEG
2020-06-16 01:53:21 +01:00
MerryMage
f3845cea9a
A32: Implement ASIMD VQSUB instruction
2020-05-30 18:19:17 +01:00
MerryMage
16ff880f8f
A32: Implement ASIMD VQADD
2020-05-30 16:09:37 +01:00
MerryMage
3a50d444dc
A32: Implement ASIMD VHSUB
2020-05-28 22:29:00 +01:00
MerryMage
205e6c5a56
A32: Implement ASIMD VRHADD
2020-05-28 22:29:00 +01:00
MerryMage
946eb03a3b
A32: Implement ASIMD VHADD
2020-05-28 22:29:00 +01:00
Lioncash
fc112e61f2
A32: Implement ASIMD modified immediate functions
...
Implements VBIC, VMOV, VMVN, and VORR modified immediate instructions.
2020-05-24 23:55:47 +01:00
Lioncash
659d78c9c4
A32: Implement ASIMD VSWP
...
A trivial one to implement, this just swaps the contents of two
registers in place.
2020-05-22 19:43:24 +01:00
MerryMage
d0b45f6150
A32: Implement ARMv8 VST{1-4} (multiple)
2020-05-17 17:01:39 +01:00
Lioncash
f42b3ad4a0
A32: Implement ASIMD VBIF (register)
2020-05-16 20:22:12 +01:00
Lioncash
ee9a81dcba
A32: Implement ASIMD VBIT (register)
2020-05-16 20:22:12 +01:00
Lioncash
d624059ead
A32: Implement ASIMD VBSL (register)
2020-05-16 20:22:12 +01:00
Lioncash
4b5e3437cf
A32: Implement ASIMD VEOR (register)
2020-05-16 20:22:12 +01:00
