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58 Commits

Author SHA1 Message Date
Lioncash
5ebf496d4e translate: Deduplicate GetDataSize() functions 
Avoids defining the same function multiple times in different files.
 2020-04-22 20:46:22 +01:00
MerryMage
642b6c31d2 A64: Implement MLA, MLS (by element), vector single/double variant 2020-04-22 20:46:22 +01:00
MerryMage
b455b566e7 A64: Implement UQXTN (vector) 2020-04-22 20:46:22 +01:00
MerryMage
3874cb37e3 A64: Implement SQXTN (vector) 2020-04-22 20:46:22 +01:00
MerryMage
f020dbe4ed A64: Implement SQXTUN 2020-04-22 20:46:22 +01:00
MerryMage
b2e4c16ef8 A64: Implement FRSQRTS (vector), single/double variant 2020-04-22 20:46:22 +01:00
Lioncash
49c7edf7c6 A64: Implement FMLA and FMLS (by element)'s double/single-precision scalar variant 2020-04-22 20:46:21 +01:00
Lioncash
c704acafe4 A64: Implement FMUL (by element)'s scalar double/single-precision variant 2020-04-22 20:46:21 +01:00
MerryMage
16061c28f3 simd_vector_x_indexed_element: Implement FMUL (by element), vector variant 2020-04-22 20:46:21 +01:00
Lioncash
593eca7fb1 A64: Implement load/store single structure instructions 
Implements LD{1, 2, 3, 4}, LD{1, 2, 3, 4}R, and ST{1, 2, 3, 4} single
structure variants.
 2020-04-22 20:46:18 +01:00
Lioncash
43e6e98c3b A64: Add missing decoding for PRFM (unscaled offset) 2020-04-22 20:46:17 +01:00
Lioncash
b719a6b3f7 A64: Implement XAR 2020-04-22 20:46:17 +01:00
MerryMage
bfba38d0b6 impl: Reorganize scalar two-register misc instructions 2020-04-22 20:46:16 +01:00
Lioncash
ab35dc0e78 A64: Implement MLS (by element) 2020-04-22 20:46:16 +01:00
Lioncash
1651e60462 A64: Implement MUL (by element) 2020-04-22 20:46:16 +01:00
MerryMage
a86d4093cd A64: Implement MLA (by element) 2020-04-22 20:46:16 +01:00
Lioncash
80e005e5b5 A64/translate: Amend I() to also handle u8 and u16 immediates 
This is necessary for instructions like SRSHR, and other related instructions.
 2020-04-22 20:46:15 +01:00
MerryMage
7969871aa3 A64: Implement FMOV (vector, immediate) and mark other SIMD modified immediate instructions as unallocated 2020-04-22 20:46:15 +01:00
Lioncash
9de60b60bb A64/translate: Amend instruction prototypes erroneously marked as taking Reg 
Makes the prototypes consistent
 2020-04-22 20:46:15 +01:00
Lioncash
84d49309b9 A64: Implement USUBW/USUBW2 2020-04-22 20:46:15 +01:00
Lioncash
e20fce6b5a A64: Implement SSUBW/SSUBW2 2020-04-22 20:46:15 +01:00
Lioncash
00af6eeab9 A64: Implement SADDW/SADDW2 2020-04-22 20:46:15 +01:00
MerryMage
8bba37089e A64: Implement UADDW 2020-04-22 20:46:15 +01:00
MerryMage
fd075d8d68 system: Raise exception for YIELD, WFE, WFI, SEV, SEVL 2020-04-22 20:46:15 +01:00
MerryMage
e3da92024e A64: Implement system registers FPCR and FPSR 2020-04-22 20:46:15 +01:00
MerryMage
b7a2c1a7df A64: Implement STXRB, STXRH, STXR, STLXRB, STLXRH, STLXR, LDXRB, LDXRH, LDXR, LDAXRB, LDAXRH, LDAXR 2020-04-22 20:46:14 +01:00
MerryMage
8756487554 A64: Partially implement MRS 2020-04-22 20:46:14 +01:00
MerryMage
5edd623b9d Implement DC instructions 2020-04-22 20:46:14 +01:00
MerryMage
5f77ab28ee A64: Implement SSHLL, SSHLL2 2020-04-22 20:46:14 +01:00
MerryMage
3738043e58 A64: Implement DUP (element), vector variant 2020-04-22 20:46:14 +01:00
MerryMage
e7041d7196 A64: Implement STR (register, SIMD&FP), LDR (register, SIMD&FP) 2020-04-22 20:46:14 +01:00
MerryMage
e858ce0b35 A64: Implement SIMD instructions XTN, XTN2 2020-04-22 20:46:13 +01:00
MerryMage
7ff280827b A64: Implement SIMD instructions USHLL, USHLL2 2020-04-22 20:46:13 +01:00
MerryMage
1d0cd95b23 A64: Implement SIMD instruction SHL 2020-04-22 20:46:13 +01:00
MerryMage
1a7b7b541a A64: Implement MOVI, MVNI, ORR (vector, immediate), BIC (vector, immediate) 
There wasn't a clean way to seperate these instructions out.
 2020-04-22 20:46:13 +01:00
MerryMage
8ab7d8175c impl: Add AdvSIMDExpandImm 2020-04-22 20:46:13 +01:00
MerryMage
eb5591859c A64: Implement FMOV (general) 2020-04-22 20:46:13 +01:00
MerryMage
dd88cee15a translate/impl: Add Vpart 2020-04-22 20:46:13 +01:00
MerryMage
b02b861242 A64: Implement STLRB, STLRH, STLR, LDARB, LDARH, LDAR 2020-04-22 20:46:13 +01:00
MerryMage
56bc7825ef A64: Implement STR{,B,H} (register), LDR{,B,H,SB,SH,SW} (register), PFRM (register) 2020-04-22 20:46:13 +01:00
MerryMage
a07c05ea51 A64: Implement STUR (SIMD&FP), LDUR (SIMD&FP) 2020-04-22 20:46:13 +01:00
MerryMage
93fcbdf1e2 A64: Implement FCMP, FCMPE 2020-04-22 20:46:13 +01:00
MerryMage
99d8ebe4d5 A64: Implement FMUL (scalar), FDIV (scalar), FADD (scalar), FSUB (scalar), FNMUL (scalar) 2020-04-22 20:46:13 +01:00
MerryMage
ed2bedec43 A64: Implement {ST,LD}{1,2,3,4} (multiple structures) 2020-04-22 20:46:13 +01:00
MerryMage
88ae7fce52 A64: Implement LDP (SIMD&FP) and STP (SIMD&FP) 2020-04-22 20:44:38 +01:00
Lioncash
67443efb62 General: Convert multiple namespace specifiers to nested namespace specifiers where applicable 
Makes namespacing a little less noisy
 2020-04-22 20:44:38 +01:00
James Rowe
41e6e659c5 A64: Implement Load/Store register (unprivileged) 2020-04-22 20:44:37 +01:00
MerryMage
6033b05ca6 A64: Implement LDR/STR (immediate, SIMD&FP) 2020-04-22 20:44:37 +01:00
MerryMage
e1df7ae621 IR: Add IR instructions A64Memory{Read,Write}128 
This implementation only works on macOS and Linux.
 2020-04-22 20:44:37 +01:00
MerryMage
a63fc6c89b A64: Implement ADD (vector, vector) 2020-04-22 20:42:46 +01:00