12 Commits

Author	SHA1	Message	Date
MerryMage	624e84fa09	Optimization: Tweak RSB	2016-08-15 14:08:06 +01:00
MerryMage	960d14d18e	Optimization: Implement Return Stack Buffer	2016-08-13 00:10:23 +01:00
MerryMage	df39308e03	TranslateArm: Implement CLREX, LDREX, LDREXB, LDREXD, LDREXH, STREX, STREXB, STREXD, STREXH, SWP, SWPB	2016-08-09 22:57:20 +01:00
MerryMage	975f011fc0	BackendX64/RegAlloc: Do not allocate RSP for guest use	2016-08-08 16:01:07 +01:00
MerryMage	aba705f6b9	BackendX64: Merge Routines into BlockOfCode	2016-08-07 18:08:48 +01:00
MerryMage	f88b1b4c2e	FPSCR: Save and restore MSCSR across supervisor call, fix MXCSR exception mask	2016-08-07 01:10:19 +01:00
MerryMage	4b31ea25a7	VFP: Implement VADD.{F32,F64}	2016-08-06 20:03:15 +01:00
MerryMage	640ce48baa	VFP: Implement {Get,Set}ExtendedRegister{32,64}	2016-08-05 19:06:10 +01:00
MerryMage	4414ec5bc8	RegAlloc: Allow allocation of XMM registers	2016-08-02 13:46:12 +01:00
MerryMage	93af160c97	arm_types: Add FPSCR to Arm::LocationDescriptor and make Arm::LocationDescriptor have a FauxO-like interface	2016-08-02 11:54:02 +01:00
MerryMage	d743adf518	Reorganisation, Import Skyeye, This is a mess	2016-07-04 17:22:11 +08:00
MerryMage	65df15633d	First Commit	2016-07-01 21:01:06 +08:00