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Commit Graph

191 Commits

Author SHA1 Message Date
MerryMage
714b0b9a8b A32/translate: Factor conditional state handling out 2021-02-07 20:41:48 +00:00
MerryMage
7e5ae6076a A32: Add arch_version option 2021-02-07 12:13:14 +00:00
Lioncash
50d81f95e5 thumb32: Implement USADA8 2021-02-07 09:57:34 +00:00
Lioncash
ed453aa52d thumb32: Implement USAD8 2021-02-07 09:57:34 +00:00
Lioncash
b07fab604f thumb32: Implement MLS 2021-02-07 09:57:34 +00:00
Lioncash
cf5058bccb thumb32: Implement MLA 2021-02-07 09:57:34 +00:00
Lioncash
153d87c843 thumb32: Implement MUL 2021-02-07 09:57:34 +00:00
MerryMage
ac9e1ccb1c A32/thumb16: Fix bug in CBZ/CBNZ 2021-02-06 21:25:24 +00:00
Lioncash
23619c8c6a thumb32: Implement SHSUB8/UHSUB8 2021-02-01 17:50:46 -05:00
Lioncash
9d2570470e thumb32: Implement SHADD8/UHADD8 2021-02-01 17:50:46 -05:00
Lioncash
afad76078d thumb32: Implement SHSUB16/UHSUB16 2021-02-01 17:50:46 -05:00
Lioncash
51b7c32d02 thumb32: Implement SHSAX/UHSAX 2021-02-01 17:50:46 -05:00
Lioncash
f0a219fcd0 thumb32: Implement SHASX/UHASX 2021-02-01 17:50:46 -05:00
Lioncash
94f8efbb03 thumb32: Implement SHADD16/UHADD16 2021-02-01 17:50:46 -05:00
Lioncash
aa49b0db89 thumb32: Implement QSUB8/UQSUB8 2021-02-01 17:50:46 -05:00
Lioncash
874ab6a7b6 thumb32: Implement QADD8/UQADD8 2021-02-01 17:50:46 -05:00
Lioncash
d923fb24c6 thumb32: Implement QSUB16/UQSUB16 2021-02-01 17:50:46 -05:00
Lioncash
416fe26df0 thumb32: Implement QSAX/UQSAX 2021-02-01 17:50:14 -05:00
Lioncash
ad7c8bd042 thumb32: Implement QASX/UQASX 2021-02-01 17:31:30 -05:00
Lioncash
f52b8f924c thumb32: Implement QADD16/UQADD16 2021-02-01 17:31:30 -05:00
Lioncash
6f593da41b thumb32: Implement SSUB8/USUB8 2021-02-01 17:31:27 -05:00
Lioncash
271354ee95 thumb32: Implement SADD8/UADD8 2021-02-01 16:44:11 -05:00
Lioncash
8f42fd5c0e thumb32: Implement SSUB16/USUB16 2021-02-01 16:41:02 -05:00
Lioncash
0e28c63456 thumb32: Implement SSAX/USAX 2021-02-01 16:36:18 -05:00
Lioncash
21e404d3ab thumb32: Implement SASX/UASX 2021-02-01 16:31:25 -05:00
Lioncash
d529417875 thumb32: Implement SADD16/UADD16 2021-02-01 16:19:33 -05:00
Lioncash
36fc596a51 thumb32: Implement QADD 2021-02-01 15:44:09 -05:00
Lioncash
cd6e4c7afd thumb32: Implement QSUB 2021-02-01 15:42:14 -05:00
Lioncash
65365ad2a3 thumb32: Implement QDADD 2021-02-01 15:39:39 -05:00
Lioncash
d96c8c662b thumb32: Implement QDSUB 2021-02-01 15:35:09 -05:00
Lioncash
c60cf921ee thumb32: Implement REV 2021-02-01 15:30:40 -05:00
Lioncash
0304dc7ce4 thumb32: Implement REV16 2021-02-01 15:27:31 -05:00
Lioncash
cee31c5274 thumb32: Implement RBIT 2021-02-01 15:20:24 -05:00
Lioncash
e2bc7eeb93 thumb32: Implement REVSH 2021-02-01 15:16:53 -05:00
Lioncash
1ad99bb9b5 thumb32: Implement SEL 2021-02-01 15:01:21 -05:00
Lioncash
8d53048750 thumb32: Implement CLZ 
Also fleshes out the generator to allow for generating thumb32
instructions as well.
 2021-02-01 14:54:04 -05:00
MerryMage
82868034d3 A32/ASIMD: Ensure decoder table is correct 
* Raise a DecoderError instead of ASSERT-ing on a decode error
* Correct ASIMD decode table
* Write a test which verifies every possible ASIMD instruction
 2020-07-05 18:45:42 +01:00
MerryMage
735738c7b6 A32: Implement ASIMD VPMAX, VPMIN (floating-point) 2020-07-04 11:04:10 +01:00
MerryMage
88e74cb2ba A32: Implement ASIMD VPMAX, VPMIN (integer) 2020-07-04 11:04:10 +01:00
MerryMage
df477c46c2 asimd_load_store_structures: VST1 undef correction 2020-07-04 11:04:10 +01:00
MerryMage
3eed024caf asimd_three_same: Ignore Q=1 for VPADD (floating-point) 2020-07-04 11:04:10 +01:00
MerryMage
896cb46c89 asimd_*: Standardize order of n and m to reduce confusion 2020-07-04 11:04:10 +01:00
Merry
4f967387c0 asimd_three_regs: Reimplement asimd_VMLAL in terms of WideInstruction 2020-06-27 13:06:46 +01:00
Merry
7997404ee7 A32: Implement ASIMD V{ADD,SUB}{W,L} 2020-06-27 12:58:47 +01:00
Merry
868bd00ab5 A32: Rearrange translators for ASIMD Three Registers 
* Separate Three Registers with Different Lengths from Same Lengths decoders
 2020-06-27 11:15:07 +01:00
MerryMage
495f58eed8 A32: Implement ASIMD VSHLL 2020-06-24 23:47:13 +01:00
MerryMage
ed48a9d7d5 A32: Implement VFPv5 VRINTX 2020-06-24 22:31:58 +01:00
Lioncash
b5df8d1ef8 A32: Implement ASIMD VQDMULL (scalar) 2020-06-23 18:19:42 +01:00
Lioncash
20a2bf29fc A32: Implement ASIMD VQRDMULH (scalar) 2020-06-23 18:19:42 +01:00
Lioncash
ab5efe8632 A32: Implement ASIMD VQDMULH (scalar) 2020-06-23 18:19:42 +01:00