381 Commits

Author SHA1 Message Date
MerryMage
7242388577 A64: Specialize arithmetic shift SBFM aliases 2020-04-22 21:07:09 +01:00
MerryMage
a13392e432 A64: Specialize sign-extension SBFM aliases 2020-04-22 21:07:09 +01:00
Lioncash
11d1114a17 A64: Implement all half-precision variants of FCMEQ 2020-04-22 21:04:22 +01:00
Lioncash
6b9bf7868a General: Correct typos is code comments 2020-04-22 21:04:22 +01:00
Lioncash
471eb77bc9 A64: Implement FRSQRTS' half-precision vector variant 2020-04-22 21:01:45 +01:00
Lioncash
f9b2862217 A64: Implement FRSQRTS' half-precision scalar variant
With the necessary machinery in place, we can now handle the
half-precision variant.
2020-04-22 21:01:45 +01:00
Merry
45864133f5 Merge pull request #478 from lioncash/stepfused
A64: Handle half-precision variants of FRECPE and FRECPS
2020-04-22 21:01:44 +01:00
Lioncash
3739d92097 A64: Implement half-precision vector variant of FRECPE 2020-04-22 21:01:44 +01:00
Lioncash
7b212ec8ae A64: Implement half-precision variant of FRSQRTE's vector variant 2020-04-22 21:01:44 +01:00
Lioncash
0945a491bd A64: Implement half-precision scalar variant of FRECPE 2020-04-22 21:01:44 +01:00
Lioncash
77c84bcf9b A64: Implement half-precision variant of FRSQRTE's scalar variant 2020-04-22 21:01:44 +01:00
Lioncash
86b7626a2f A64: Implement half-precision vector variant of FRECPS 2020-04-22 21:01:44 +01:00
Lioncash
de43f011a7 A64: Implement half-precision scalar variant of FRECPS 2020-04-22 21:01:44 +01:00
Lioncash
d7f394fc1a A64: Enable half-precision vector FRINT* variants 2020-04-22 21:01:44 +01:00
Merry
cb9a1b18b6 Merge pull request #475 from lioncash/muladd
A64: Enable half-precision variants of floating-point multiply-add instructions
2020-04-22 21:01:44 +01:00
Lioncash
9a58c3f1c7 A64: Implement FMLA/FMLS' half-precision vector indexed variants 2020-04-22 21:01:44 +01:00
Lioncash
9dcc04e106 A64: Implement SQSHLU's scalar variant 2020-04-22 21:01:44 +01:00
Lioncash
1fdd3ef8a0 A64: Implement FMLA/FMLS' half-precision scalar indexed variants 2020-04-22 21:01:44 +01:00
Lioncash
2d59d10ac8 A64: Implement SQSHLU's vector variant
The vector shift by immediate category is now fully implemented.
2020-04-22 21:01:44 +01:00
Lioncash
d6606deda2 A64: Implement half-precision vector variants of FMLA/FMLS 2020-04-22 21:01:44 +01:00
Lioncash
3b46b4a37d A64: Implement SQRDMULH's scalar vector variant
Implements the scalar variant in terms of the vector variant for the
time being.
2020-04-22 21:01:43 +01:00
Lioncash
6c2c68bce6 A64: Implement FCMLA's indexed element variant
With this, all of the instructions introduced with ARMv8.3-CompNum have
an implementation.
2020-04-22 21:00:47 +01:00
Lioncash
b1b4487e4d A64: Implement UQSHL (immediate)'s scalar variant
Like SQSHL's immediate scalar variant, we can also implement UQSHL's
immediate scalar variant in terms of the vector variant for the time
being.
2020-04-22 21:00:47 +01:00
Lioncash
3649dc6d9a A64: Implement scalar variant of SQSHL (immediate)
This can be handled in terms of the vector variant for the time being.
2020-04-22 21:00:47 +01:00
Merry
c1ce94872d Merge pull request #455 from lioncash/sqrdmulh-scalar
A64: Implement SQRDMULH and SQDMULL's scalar indexed variants
2020-04-22 20:58:11 +01:00
Lioncash
97dd3d0596 A64: Implement SQRDMULH's scalar indexed element variant 2020-04-22 20:58:11 +01:00
Lioncash
692aba91b6 A64: Implement SQDMULL{2}'s scalar indexed element variant 2020-04-22 20:58:11 +01:00
Lioncash
c043b831d5 A64: Implement SQDMULL{2}'s by-element variant 2020-04-22 20:58:11 +01:00
Lioncash
72af5a3dff simd_scalar_x_indexed_element: Factor out index and Vm argument construction
This will be useful in the implementations of SQRDMULH and SQDMULL{2} as
well.
2020-04-22 20:58:11 +01:00
Lioncash
224ff0afaa A64: Implement SQRDMULH's by-index vector variant 2020-04-22 20:58:11 +01:00
Lioncash
3a3542414b A64: Implement FRECPX's half-precision floating point variant 2020-04-22 20:58:11 +01:00
Lioncash
126c29a9e9 A64: Implement SQSHRN, SQSHRUN, and UQSHRN's scalar variants
These can just be implemented in terms of the vector variants for the
time being.
2020-04-22 20:58:11 +01:00
Merry
bbd5330ad2 Merge pull request #447 from lioncash/flag
A64: Implement CFINV, RMIF, AXFlag and XAFlag
2020-04-22 20:58:11 +01:00
Merry
fb039e232c Merge pull request #442 from lioncash/fcvtxn
A64: Implement scalar and vector variants of FCVTXN
2020-04-22 20:58:11 +01:00
Merry
4f937c1ee1 Merge pull request #446 from lioncash/sqshl
A64: Implement scalar variants of SQSHL (register) and UQSHL (register)
2020-04-22 20:58:11 +01:00
Lioncash
aa22db534b A64: Implement AXFlag and XAFlag 2020-04-22 20:58:11 +01:00
Merry
d74cccbc84 Merge pull request #445 from lioncash/sqrt
A64: Implement single and double-precision vector variant of FSQRT
2020-04-22 20:58:11 +01:00
Lioncash
20ffe568d0 A64: Implement RMIF 2020-04-22 20:58:11 +01:00
Lioncash
51b526e453 A64: Implement CFINV 2020-04-22 20:58:11 +01:00
Lioncash
d3515279df A64: Implement the vector version of FCVTXN 2020-04-22 20:58:10 +01:00
Lioncash
17aea0b997 A64: Implement UQSHL (register)'s scalar variant
This can be implemented in terms of the vector variant.
2020-04-22 20:58:10 +01:00
Lioncash
c99d4b762e A64: Implement single and double-precision vector variant of FSQRT 2020-04-22 20:58:10 +01:00
Lioncash
54e0b487f3 A64: Rearrange flag format/manipulation instructions
Gives these instructions better categorical labeling.
2020-04-22 20:58:10 +01:00
Lioncash
4339a8fff6 A64: Implement the scalar version of FCVTXN 2020-04-22 20:58:10 +01:00
Lioncash
35ddf68ad5 A64: Implement SQSHL (register)'s scalar variant
We can implement this in terms of the vector variant.
2020-04-22 20:58:10 +01:00
Merry
40b081438a Merge pull request #439 from lioncash/fcmla
A64: Implement FCADD and FCMLA
2020-04-22 20:58:10 +01:00
Merry
d91192681a Merge pull request #438 from lioncash/fmulx
A64: Implement scalar double/single precision FMULX (by element)
2020-04-22 20:58:10 +01:00
Lioncash
ed29ef8cca A64: Implement FCMLA 2020-04-22 20:58:10 +01:00
Merry
9f11720a69 Merge pull request #437 from lioncash/frecpx
A64: Implement FRECPX (single, double precision)
2020-04-22 20:58:10 +01:00
Lioncash
bdcea0b0dc A64: Implement scalar double/single precision FMULX (by element) 2020-04-22 20:58:10 +01:00