2478 Commits

Author SHA1 Message Date
Merry
7e046357ff backend/arm64: Initial implementation of register allocator 2022-10-18 15:04:30 +01:00
Merry
3bf2b0aba9 backend/arm64: Adjust how relocations are stored 2022-10-18 15:04:30 +01:00
Merry
e0f091b6a6 backend/arm64: void* -> CodePtr 2022-10-18 15:04:30 +01:00
Merry
f6e80f1e0e backend/arm64: First dummy code execution 2022-10-18 15:04:30 +01:00
Merry
d877777c50 backend/arm64: Initial framework 2022-10-18 15:04:30 +01:00
Wunkolo
e886bfb7c1 backend/x64: Fix FixupLUT argument order
The last two arguments(fixup response response for finite values) are
neg-pos, not pos-neg. Found this out while re-using this function for
some math stuff. Thankfully nothing currently uses this fixup response
at the moment.
2022-09-30 23:10:21 +01:00
Merry
af51845a53 decoder_detail: Workaround #708 2022-09-02 21:16:43 +01:00
Bart Ribbers
e49fee0ca1 block_of_code: rename PAGE_SIZE to DYNARMIC_PAGE_SIZE to prevent use of reserved name
PAGE_SIZE is a kernel symbol and depending on the libc in use, it will
"leak". In this case dynarmic was using it's own PAGE_SIZE and in
combination with the Musl libc the compiler would complain it was overwriting
the kernel symbol
2022-08-25 23:32:18 +01:00
Merry
bf422a190a decoder_detail: Simplify DYNARMIC_DECODER_GET_MATCHER 2022-08-21 18:22:14 +01:00
Merry
c60fd3f0ac block_of_code: Fix running under Rosetta
Rosetta doesn't have accurate emulation of the sahf instruction
2022-08-05 23:43:01 +01:00
Merry
a38966a874 block_of_code: Extract flag loading into a function
LoadRequiredFlagsForCondFromRax
2022-08-05 23:42:19 +01:00
Merry
d7bd5bb7a7 emit_x64: Use movzx(eax, ah) instead of emitting byte equivalent
Emission fixed in xbyak v6.61
2022-07-31 17:52:35 +01:00
Merry
f33c6f062b Revert "block_of_code: Refactor MConst to Xmm{B}Const"
This reverts commit 5d9b720189a64eec7f35f844320d0b30ca3997f3.

Obscure bugs resulting from this commit due to assumptions regarding zero-extension of higher bits.
2022-07-27 20:31:08 +01:00
Merry
fbdcfeab99 emit_x64_packed: Do not use XmmBConst here
Broadcasting is inappropriate
2022-07-27 20:14:49 +01:00
Merry
1f51dceb60 Update for fmt 9.0.0 2022-07-26 11:20:47 +01:00
Merry
82d71b850e a32_emit_x64: Bugfix for A32GetCpsr for non-FastBMI2
Incorrect loading of E and T flags
2022-07-26 10:44:30 +01:00
Merry
a2b3199adf Convert NZCV to C flag where able 2022-07-23 11:46:07 +01:00
Merry
6bcc424e1a emit_x64_vector: Ensure FPSR.QC is set even if output is invalidated 2022-07-20 19:44:39 +01:00
Merry
34cb465fc7 translate_thumb: IsThumb16: Mask not required 2022-07-20 17:34:31 +01:00
Merry
72c87d11e4 a32_get_set_elimination_pass: Correct insertion point 2022-07-20 16:53:48 +01:00
Merry
da2b1c5724 a32_get_set_elimination_pass: Convert NZ to NZC 2022-07-20 16:45:14 +01:00
Merry
6f106602ba a32_get_set_elimination_pass: Add option to disable NZC -> NZ conversion 2022-07-20 16:42:39 +01:00
Merry
52aa68c31c backend/x64: Fixup NZ flag emission 2022-07-20 14:58:28 +01:00
Merry
b97147e187 a32_get_set_elimination_pass: Reduce NZC to 00C 2022-07-20 14:44:33 +01:00
Merry
03dcc3fa50 a32_get_set_elimination_pass: Reduce NZC to NZ where possible 2022-07-20 14:08:41 +01:00
Merry
cf08130f2c A32: Condense flag handling
Remove individual flag handlers, and handle them in chuks where able, to produce more optimal code.
2022-07-19 22:05:13 +01:00
Merry
2e1ab36240 microinstruction: Also track MostSignificantBit and IsZero{32,64} as pseudoops 2022-07-19 22:02:56 +01:00
Merry
ac19912fe7 microinstruction: Optimize storage of associated pseudooperation 2022-07-19 22:02:18 +01:00
Merry
51a89dbb7a A64CallbackConfigPass: Ensure IR instructions emitted by this pass have correct location descriptors attached 2022-07-17 22:42:56 +01:00
Merry
da5d06c32a backend/x64: Remove unused member halt_requested from StackLayout 2022-07-15 15:19:01 +01:00
Merry
840982be95 block_of_code: Remove far code machinery 2022-07-14 08:58:00 +01:00
Merry
dd60f4b7d8 emit_x64_memory: Use deferred emits 2022-07-14 08:58:00 +01:00
Merry
0d1e4fc4a8 a32_emit_x64: Remove use of far code from EmitTerminalImpl LinkBlock 2022-07-14 08:58:00 +01:00
Merry
36f6114559 emit_x64_vector_floating_point: Use deferred emits 2022-07-14 08:58:00 +01:00
Merry
7d5e078baa emit_x64_floating_point: MSVC fixup 2022-07-14 08:58:00 +01:00
Merry
11ba75b7f0 emit_x64_floating_point: Use deferred emits 2022-07-14 08:58:00 +01:00
Merry
6c38ed8a89 emit_x86: Introduce the concept of deferred emits
Remove the concept of the far code region
2022-07-14 08:58:00 +01:00
Merry
b6ddeeea0f Implement memory aborts 2022-07-13 12:38:03 +01:00
Merry
285e617e35 Revert "frontend: Add option to halt after memory accesses (#682)"
This reverts commit 5ad1d02351bf4fee681a3d701d210b419f41a505.
2022-07-13 12:34:37 +01:00
Merry
7016ace72b llvm_disassemble: Add hex output 2022-07-12 19:20:25 +01:00
Merry
cd85b7fdaa emit_x64: Fix bugs in fast dispatcher
* We failed to invalidate entries if there are no patches required for a location descriptor.
* Bug in A64 hashing code (rbx instead of rbp).
* Bug in A32 and A64 lookup code (inconsistent choice of key: PC vs IR::LocationDescriptor).
* Test case added.
2022-07-11 16:06:54 +01:00
Wunkolo
a5318c775c constant_pool: Use std::span to manage pool
Simplifies some raw pointer arithmetic and type-usage into the new
`ConstantT` type.
2022-07-07 23:46:21 +01:00
Wunkolo
5d9b720189 block_of_code: Refactor MConst to Xmm{B}Const
`MConst` is refactored into `XmmConst` to clearly communicate the
addressable space of the newly allocated 16-byte memory constant.
`GetVectorOf` is elevated into a globally available `XmmBConst` function
that "broadcasts" bits of the input-value into n-bit elements that span
the width of the Xmm-constant.

`emit_x64_floating_point` will utilize the same 16-byte
broadcasted-constants to encourage more cache-hits within the
constant-pool between vector and non-vector code.
2022-07-07 23:46:05 +01:00
Liam
02c8b434c7 interface: allow clear of previously-signaled halt 2022-07-07 23:45:09 +01:00
Wunkolo
4d78d167d6 emit_x64_{vector_}floating_point: Add AVX512 implementation for ForceToDefaultNaN
`vfpclassp* k, xmm, i8` has better latency(4->3) and allocates better
execution ports(01->5) that are out of the way of ALU-ports than
`vcmpunordp* xmm, xmm, xmm`(`vcmpp* xmm, xmm, xmm, i8`) and removes the
pipeline dependency on `xmm0` in favor AVX512 `k`-mask registers.

`vblendmp* xmm, k, xmm, mem` is about the same throughput and latency as
`blendvp* xmm. mem` but has the benefit of embedded broadcasts to reduce
memory bandwidth(32/64-bit read rather than 128-bit) and lends itself to
a future size optimization feature of `constant_pool`.
2022-06-22 00:08:49 +01:00
Wunkolo
6367a26e62 emit_x64_{vector_}floating_point: Add AVX512 implementation for DenormalsAreZero
Both single and double precision floating point numbers as well as the
packed and unpacked version of this instruction will be able to use the
same memory constant. This takes advantage of the fact that `VFIXUPIMM*`
doesn't just copy from the source, but it will convert to `0.0` if it
turns out that it is a denormal and the `MXCSR.DAZ` flag is set.

```
tsrc[31:0]←((src1[30:23] = 0) AND (MXCSR.DAZ =1)) ? 0.0 : src1[31:0]
...
CASE(token_response[3:0]) {
    ...
    0001: dest[31:0]←tsrc[31:0]; ; pass through src1 normal input value, denormal as zero
    ...
```
2022-06-22 00:08:14 +01:00
Wunkolo
3ed2aebb20 backend/x64: Update FpFixup constants with denormal behavior
There is an important subtlety that should be documented here. All the
operands of `FpFixup` that read from the `Src` register actually do a
`DAZ` operation if `MXCSR.DAZ` is set.
2022-06-22 00:08:14 +01:00
Merry
d40557b751 A32/A64: Allow std::nullopt from MemoryReadCode
Raise a fault at runtime if this block is executed
2022-06-21 21:41:27 +01:00
liamwhite
5ad1d02351
frontend: Add option to halt after memory accesses (#682)
Intended to be used for library users wishing implement accurate memory watchpoints.

* A32: optionally make memory instructions the end of basic blocks
* A64: optionally make memory instructions the end of basic blocks
* Make memory halt checking a user configurable
* oops
2022-06-16 18:09:04 +01:00
SachinVin
46989efc2b asimd_one_reg_modified_immediate.cpp: Rename mvn to mvn_ 2022-05-28 13:27:14 +01:00