11 Commits

Author	SHA1	Message	Date
Lioncash	8316d231e9	A32: Implement barrier instructions introduced in ARMv7 ... Provides basic implementations of the barrier instruction introduced within ARMv7. Currently these simply mirror the behavior of the AArch64 equivalents.	2020-04-22 21:02:46 +01:00
Lioncash	ee973f13c7	frontend/A32/ir_emitter: Mark PC() and AlignPC() as const-qualified member functions ... These don't modify instance state, so they can be const-qualified member functions.	2020-04-22 20:57:38 +01:00
MerryMage	aac5af50e2	IR: FPCompare{32,64} now return NZCV flags instead of implicitly setting them	2020-04-22 20:46:13 +01:00
MerryMage	f023bbb893	A32: Add ExceptionRaised IR instruction and use it	2020-04-22 20:46:12 +01:00
Lioncash	67443efb62	General: Convert multiple namespace specifiers to nested namespace specifiers where applicable ... Makes namespacing a little less noisy	2020-04-22 20:44:38 +01:00
MerryMage	5eb0bdecdf	IR: Simplify types. F32 -> U32, F64 -> U64, F128 -> U128 ... ARM's Architecture Specification Language doesn't distinguish between floats and integers as much as we do. This makes some things difficult to implement. Since our register allocator is now capable of allocating values to XMMs and GPRs as necessary, the Transfer IR instructions are no longer necessary as they used to be and they can be removed.	2020-04-22 20:42:46 +01:00
MerryMage	61125d6dd1	A64/translate: Add TranslateSingleInstruction function	2020-04-22 20:42:45 +01:00
MerryMage	f61da0b5a9	IR: Compile-time type-checking of IR	2020-04-22 20:39:27 +01:00
MerryMage	9d15e0a8e1	Final A32 refactor	2020-04-22 20:39:27 +01:00
MerryMage	8bef20c24d	IR: Split off A32 specific opcodes	2020-04-22 20:33:32 +01:00
MerryMage	b1f0cf9278	A32: Split off A32 specific IREmitter	2020-04-22 20:33:32 +01:00