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92 Commits

Author SHA1 Message Date
emuplz
8728444af8 added support for instruction ic ivau 2021-02-17 20:38:06 +00:00
Lioncash
1900df5340 frontend: Relocate advanced SIMD expansion to a common file 
Deduplicates code a little bit.
 2020-05-24 23:55:47 +01:00
Fernando Sahmkow
97b9d3e058 Exclusive Monitor: Rework exclusive monitor interface. 2020-05-03 01:40:37 +01:00
MerryMage
a8a712c801 Relicense to 0BSD 2020-04-23 15:45:57 +01:00
MerryMage
7242388577 A64: Specialize arithmetic shift SBFM aliases 2020-04-22 21:07:09 +01:00
MerryMage
a13392e432 A64: Specialize sign-extension SBFM aliases 2020-04-22 21:07:09 +01:00
Lioncash
af3614553b A64/impl: Move AccType and MemOp enum into general IR emitter header 
These will be used by both frontends in the future, so this performs the
migratory changes separate from the changes that will make use of them.
 2020-04-22 21:04:23 +01:00
Lioncash
4f47861669 A64/translate/impl: Mark DecodeBitMasks and AdvSIMDExpandImm as static 
These don't rely on instance state to perform their behavior. They're
just helper functions.
 2020-04-22 21:04:22 +01:00
Lioncash
182ceb2807 General: Make parameter names from declarations and implementations consistent 
Most of the time when this occurs, it's a bug. Thankfully this isn't the
case. However, we can resolve these cases to make the codebase more
consistent.
 2020-04-22 21:04:22 +01:00
Lioncash
6b9bf7868a General: Correct typos is code comments 2020-04-22 21:04:22 +01:00
Lioncash
8103652a91 frontend: Move imm.h to the top-level directory of the frontends 
Preparation to utilize the immediate type within the A32 backend as
well, which will allow eliminating numerous type aliases like Imm4,
Imm5, etc.
 2020-04-22 21:02:46 +01:00
Merry
c1ce94872d Merge pull request #455 from lioncash/sqrdmulh-scalar 
A64: Implement SQRDMULH and SQDMULL's scalar indexed variants
 2020-04-22 20:58:11 +01:00
Lioncash
692aba91b6 A64: Implement SQDMULL{2}'s scalar indexed element variant 2020-04-22 20:58:11 +01:00
Lioncash
c043b831d5 A64: Implement SQDMULL{2}'s by-element variant 2020-04-22 20:58:11 +01:00
Lioncash
dd7433f9d3 A64: Amend prototypes of some SIMD scalar shift by immediate opcodes 
These take a vector for a destination.
 2020-04-22 20:58:11 +01:00
Merry
fb039e232c Merge pull request #442 from lioncash/fcvtxn 
A64: Implement scalar and vector variants of FCVTXN
 2020-04-22 20:58:11 +01:00
Lioncash
d3515279df A64: Implement the vector version of FCVTXN 2020-04-22 20:58:10 +01:00
Lioncash
54e0b487f3 A64: Rearrange flag format/manipulation instructions 
Gives these instructions better categorical labeling.
 2020-04-22 20:58:10 +01:00
Lioncash
bfaeb08d3c A64: Implement LDNP/STNP 
LDNP and STNP indicate that a memory access is non-temporal/streaming
(i.e. unlikely to be repeated), allowing data caching to not be
performed. However, given this is only a hint, we can treat these two
instructions as regular LDP and STP instructions for the time being.
 2020-04-22 20:58:10 +01:00
V.Kalyuzhny
764a93bf5a Switch boost::optional to std::optional 2020-04-22 20:57:37 +01:00
Lioncash
f1a66c37ba a64: Add ARMv8.4+ instructions encodings to the encoding table 
Keeps the table up to date with the ARM specification.
 2020-04-22 20:57:37 +01:00
Lioncash
ab60720418 A64/translate/impl: Make signatures consistent for unimplemented by-element SIMD variants 
Makes them all consistent, so it isn't necessary to change the
prototypes over when implementing them.
 2020-04-22 20:55:06 +01:00
MerryMage
a9ffcf08b1 A64: Implement SQDMULL (vector), vector variant 2020-04-22 20:55:06 +01:00
Lioncash
9a3d38d2ee A64: Implement SMLAL{2}, SMLSL{2}, UMLAL{2}, and UMLSL{2}'s vector by-element variants 
We can simply modify the general function made for SMULL{2} and
UMULL{2}'s by-element variants to also handle the other multiply-based
by-element variants.
 2020-04-22 20:55:05 +01:00
Lioncash
6ccfbc9b39 A64: Implement UMULL{2}'s vector by-element variant 2020-04-22 20:55:05 +01:00
Lioncash
58e21f175c A64: Implement SMULL{2}'s vector by-element variant 2020-04-22 20:55:05 +01:00
Lioncash
f5fb496e7e A64: Implement SQDMULH's by-element scalar variant 2020-04-22 20:53:46 +01:00
Lioncash
40f0576995 A64: Implement SQDMULH's by-element vector variant 2020-04-22 20:53:46 +01:00
MerryMage
3b13f1eb12 A64/translate: Standardize arguments of helper functions 
Don't pass in IREmitter when TranslatorVisitor is already available.
 2020-04-22 20:53:45 +01:00
Lioncash
3d465e2c36 A64: Implement SQXTN, SQXTUN, and UQXTN's scalar variants 
We can implement these in terms of the vector variants
 2020-04-22 20:53:45 +01:00
Lioncash
4ff39c6ea8 A64: Implement SDOT and UDOT's (by element) variants 
Gets all of the dot product instructions out of the way.
 2020-04-22 20:53:45 +01:00
MerryMage
0c18b85c27 A64: Implement TBL and TBX 2020-04-22 20:53:45 +01:00
MerryMage
cd40e4dae0 A64/translate: Allow for unpredictable behaviour to be defined 2020-04-22 20:53:45 +01:00
MerryMage
f2393488fe A64: Implement SQADD and SQSUB, scalar variant 2020-04-22 20:46:23 +01:00
Lioncash
5ebf496d4e translate: Deduplicate GetDataSize() functions 
Avoids defining the same function multiple times in different files.
 2020-04-22 20:46:22 +01:00
MerryMage
642b6c31d2 A64: Implement MLA, MLS (by element), vector single/double variant 2020-04-22 20:46:22 +01:00
MerryMage
b455b566e7 A64: Implement UQXTN (vector) 2020-04-22 20:46:22 +01:00
MerryMage
3874cb37e3 A64: Implement SQXTN (vector) 2020-04-22 20:46:22 +01:00
MerryMage
f020dbe4ed A64: Implement SQXTUN 2020-04-22 20:46:22 +01:00
MerryMage
b2e4c16ef8 A64: Implement FRSQRTS (vector), single/double variant 2020-04-22 20:46:22 +01:00
Lioncash
49c7edf7c6 A64: Implement FMLA and FMLS (by element)'s double/single-precision scalar variant 2020-04-22 20:46:21 +01:00
Lioncash
c704acafe4 A64: Implement FMUL (by element)'s scalar double/single-precision variant 2020-04-22 20:46:21 +01:00
MerryMage
16061c28f3 simd_vector_x_indexed_element: Implement FMUL (by element), vector variant 2020-04-22 20:46:21 +01:00
Lioncash
593eca7fb1 A64: Implement load/store single structure instructions 
Implements LD{1, 2, 3, 4}, LD{1, 2, 3, 4}R, and ST{1, 2, 3, 4} single
structure variants.
 2020-04-22 20:46:18 +01:00
Lioncash
43e6e98c3b A64: Add missing decoding for PRFM (unscaled offset) 2020-04-22 20:46:17 +01:00
Lioncash
b719a6b3f7 A64: Implement XAR 2020-04-22 20:46:17 +01:00
MerryMage
bfba38d0b6 impl: Reorganize scalar two-register misc instructions 2020-04-22 20:46:16 +01:00
Lioncash
ab35dc0e78 A64: Implement MLS (by element) 2020-04-22 20:46:16 +01:00
Lioncash
1651e60462 A64: Implement MUL (by element) 2020-04-22 20:46:16 +01:00
MerryMage
a86d4093cd A64: Implement MLA (by element) 2020-04-22 20:46:16 +01:00