16 Commits

Author	SHA1	Message	Date
MerryMage	960d14d18e	Optimization: Implement Return Stack Buffer	2016-08-13 00:10:23 +01:00
MerryMage	1029fd27ce	Update documentation (2016-08-12)	2016-08-12 18:17:31 +01:00
MerryMage	94b99f5949	Common: Add an intrusive list implementation; remove use of boost::intrusive::list.	2016-08-06 22:23:01 +01:00
MerryMage	4d127c19dd	Common: Add a memory pool implementation, remove use of boost::pool	2016-08-06 20:41:00 +01:00
MerryMage	640ce48baa	VFP: Implement {Get,Set}ExtendedRegister{32,64}	2016-08-05 19:06:10 +01:00
MerryMage	01cfaf0286	IR: Properly support Identity in IR::Value	2016-08-05 14:09:10 +01:00
MerryMage	4414ec5bc8	RegAlloc: Allow allocation of XMM registers	2016-08-02 13:46:12 +01:00
MerryMage	be87038ffd	IROpt: Port get/set elimination pass to current IR	2016-08-02 11:51:05 +01:00
MerryMage	51448aa06d	More Speed	2016-07-22 23:55:00 +01:00
MerryMage	5fbfc6c155	Implement some simple IR optimizations (get/set eliminiation and DCE)	2016-07-21 21:48:45 +01:00
MerryMage	c18a3eeab4	Better MSVC support ... * Avoiding use of templated variables. * Now compling on MSVC with /WX (warnings as errors). * Fixed all MSVC warnings. * Fixed MSVC source_groups.	2016-07-18 10:38:22 +01:00
MerryMage	7d7751c157	Allow IR blocks to require a cond for block entry. ... * IR: Add cond, cond_failed. * backend_x64/EmitX64: Implement EmitCondPrelude	2016-07-14 12:52:53 +01:00
MerryMage	d0b48bfb59	Implement thumb1_ADD_reg_t1 and thumb1_ADD_reg_t2	2016-07-08 17:44:51 +08:00
MerryMage	5711e62419	Implement terminal instructions	2016-07-07 17:53:09 +08:00
MerryMage	14388ea690	Proper implementation of Arm::Translate	2016-07-04 21:37:50 +08:00
MerryMage	d743adf518	Reorganisation, Import Skyeye, This is a mess	2016-07-04 17:22:11 +08:00