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110 Commits

Author SHA1 Message Date
MerryMage
82868034d3 A32/ASIMD: Ensure decoder table is correct 
* Raise a DecoderError instead of ASSERT-ing on a decode error
* Correct ASIMD decode table
* Write a test which verifies every possible ASIMD instruction
 2020-07-05 18:45:42 +01:00
MerryMage
735738c7b6 A32: Implement ASIMD VPMAX, VPMIN (floating-point) 2020-07-04 11:04:10 +01:00
MerryMage
88e74cb2ba A32: Implement ASIMD VPMAX, VPMIN (integer) 2020-07-04 11:04:10 +01:00
Merry
7997404ee7 A32: Implement ASIMD V{ADD,SUB}{W,L} 2020-06-27 12:58:47 +01:00
Merry
868bd00ab5 A32: Rearrange translators for ASIMD Three Registers 
* Separate Three Registers with Different Lengths from Same Lengths decoders
 2020-06-27 11:15:07 +01:00
MerryMage
495f58eed8 A32: Implement ASIMD VSHLL 2020-06-24 23:47:13 +01:00
Lioncash
b5df8d1ef8 A32: Implement ASIMD VQDMULL (scalar) 2020-06-23 18:19:42 +01:00
Lioncash
20a2bf29fc A32: Implement ASIMD VQRDMULH (scalar) 2020-06-23 18:19:42 +01:00
Lioncash
ab5efe8632 A32: Implement ASIMD VQDMULH (scalar) 2020-06-23 18:19:42 +01:00
MerryMage
48b2ffdde9 A32: Implement ASIMD VQMOVUN, VQMOVN 2020-06-22 20:02:52 +01:00
Lioncash
dd8d5497da A32: Implement ASIMD VQRDMULH 2020-06-22 17:31:57 +01:00
Lioncash
0b7a111b54 A32: Implement ASIMD VQDMULH 2020-06-22 17:31:57 +01:00
Lioncash
39488e4aad A32: Implement ASIMD VRSHRN 2020-06-21 23:15:43 +01:00
Lioncash
86b0e5c1c5 A32: Implement ASIMD VQSHRN 2020-06-21 23:15:43 +01:00
Lioncash
85222e3e65 A32: Implement ASIMD VQSHRUN 
We can leverage ShiftRightNarrowing() to implement this.
 2020-06-21 23:15:43 +01:00
MerryMage
562a98bcf9 A32: Implement ASIMD VCVT (between floating-point and fixed-point) 2020-06-21 20:23:40 +01:00
MerryMage
6f56043a73 A32: Implement ASIMD VFMA, VFMS 2020-06-21 20:21:53 +01:00
Lioncash
aa0358d324 A32: Implement ASIMD VMLAL/VMLSL (integer) 2020-06-21 20:03:19 +01:00
Lioncash
eab26b404a A32: Implement ASIMD VABAL 2020-06-21 20:01:08 +01:00
Lioncash
98581839ca A32: Implement ASIMD VABDL 2020-06-21 19:55:00 +01:00
MerryMage
db85e7ced5 asimd: Add missing three registers of different lengths instructions 2020-06-21 19:54:32 +01:00
Lioncash
95919594d1 A32: Implement ASIMD VQSHL/VQSHLU (immediate) 2020-06-21 19:26:30 +01:00
MerryMage
3557576ece A32: Implement ASIMD AESD, AESE, AESIMC, AESMC 2020-06-21 18:39:57 +01:00
MerryMage
df58a429ee A32: Implement ASIMD VQRSHRN 2020-06-21 17:41:18 +01:00
MerryMage
589d717af5 A32: Implement ASIMD VQRSHRUN 2020-06-21 17:41:18 +01:00
MerryMage
e009d99924 A32: Implement ASIMD VSHRN 2020-06-21 17:41:18 +01:00
MerryMage
8f0f1cfd66 A32: Implement ASIMD VST{1,2,3,4} (single n-element structure from one lane) 2020-06-21 16:27:33 +01:00
MerryMage
5a597f415c A32: Implement A32 VLD{1,2,3,4} (single n-element structure to one lane) 2020-06-21 16:22:43 +01:00
MerryMage
3202e4c539 A32: Implement ASIMD VLD{1,2,3,4} (single n-element structure to all lanes) 2020-06-21 15:25:26 +01:00
MerryMage
809dfe9c54 A32: Implement ASIMD VCVT (between floating-point and integer) 2020-06-21 14:28:25 +01:00
MerryMage
33a81dae68 asimd: VEXT was being shadowed 2020-06-21 13:12:19 +01:00
MerryMage
bf093395d8 A32: Implement ASIMD VMOVN 2020-06-21 12:35:39 +01:00
MerryMage
c7785cd982 A32: Implement ASIMD VUZP and VZIP 2020-06-21 12:34:55 +01:00
MerryMage
603cd09c8f A32: Implement ASIMD VTRN 2020-06-21 12:14:13 +01:00
MerryMage
9cc11681dc A32: Implement ASIMD VMLAL, VMLSL, VMULL (scalar) 2020-06-21 10:31:30 +01:00
MerryMage
69a1d58a2b A32: Implement ASIMD VMULL 2020-06-21 10:00:24 +01:00
Lioncash
8c23f02330 A32: Implement ASIMD VABD 2020-06-21 07:54:21 +01:00
Lioncash
fc1633a2ea A32: Implement ASIMD VABA 2020-06-21 07:54:21 +01:00
Lioncash
bdb92f7055 asimd: Split out VABA/VABD decoders 
These differ in bit encodings anyway
 2020-06-21 07:54:21 +01:00
Lioncash
230fa02648 A32: Implement ASIMD VMLA/VMLS (scalar) 
While we're at it, we can join the implementation of VMUL into a common
function.
 2020-06-21 07:51:17 +01:00
MerryMage
239ee289cf A32: Implement VDUP (scalar) 2020-06-21 00:22:42 +01:00
Lioncash
a8efe3f0f5 A32: Implement ASIMD VACGE/VACGT 2020-06-21 00:02:48 +01:00
Lioncash
e319257ec0 A32: Implement VCEQ/VCGE/VCGT (floating point) 2020-06-21 00:02:48 +01:00
Lioncash
faefb264a6 A32: Implement ASIMD VCEQ (integer) 2020-06-21 00:02:48 +01:00
Lioncash
7276993352 A32: Implement ASIMD VCGE (integer) 2020-06-21 00:02:48 +01:00
Lioncash
7292320445 A32: Implement ASIMD VCGT (integer) 2020-06-21 00:02:48 +01:00
MerryMage
8bbc9fdbb6 A32: Implement ASIMD VTBX 2020-06-20 22:35:31 +01:00
Lioncash
06f7229c57 A32: Implement ASIMD VPADAL (integer) 2020-06-20 22:28:47 +01:00
Lioncash
266c6a2000 A32: Implement ASIMD VPADDL (integer) 2020-06-20 22:28:47 +01:00
Lioncash
4bb286ac23 A32: Implement ASIMD VPADD (integer) 2020-06-20 21:22:14 +01:00