32 Commits

Author	SHA1	Message	Date
MerryMage	a07c05ea51	A64: Implement STUR (SIMD&FP), LDUR (SIMD&FP)	2020-04-22 20:46:13 +01:00
MerryMage	93fcbdf1e2	A64: Implement FCMP, FCMPE	2020-04-22 20:46:13 +01:00
MerryMage	99d8ebe4d5	A64: Implement FMUL (scalar), FDIV (scalar), FADD (scalar), FSUB (scalar), FNMUL (scalar)	2020-04-22 20:46:13 +01:00
MerryMage	ed2bedec43	A64: Implement {ST,LD}{1,2,3,4} (multiple structures)	2020-04-22 20:46:13 +01:00
Lioncash	a5c4fbc783	A64: Implement AESIMC and AESMC	2020-04-22 20:46:13 +01:00
Lioncash	af1384d700	A64: Implement CRC32	2020-04-22 20:46:12 +01:00
Lioncash	7ffbebf290	A64: Implement CRC32C	2020-04-22 20:46:12 +01:00
Lioncash	7734cf1050	A64: Implement EXTR	2020-04-22 20:46:12 +01:00
MerryMage	88ae7fce52	A64: Implement LDP (SIMD&FP) and STP (SIMD&FP)	2020-04-22 20:44:38 +01:00
MerryMage	75756137c6	A64: Implement CMEQ (register, vector)	2020-04-22 20:44:38 +01:00
Fernando Sahmkow	e0c12ec2ad	A64: Implemented EOR (vector), ORR (vector, register) and ORN (vector) Instructions (#142)	2020-04-22 20:44:38 +01:00
James Rowe	ae880d8391	A64: Fix bugs and address review comments	2020-04-22 20:44:38 +01:00
James Rowe	41e6e659c5	A64: Implement Load/Store register (unprivileged)	2020-04-22 20:44:37 +01:00
FernandoS27	ab84524806	Implemented SDIV and UDIV instructions	2020-04-22 20:44:37 +01:00
MerryMage	6033b05ca6	A64: Implement LDR/STR (immediate, SIMD&FP)	2020-04-22 20:44:37 +01:00
MerryMage	3caf192f60	A64: Implement DUP (general)	2020-04-22 20:44:37 +01:00
Lioncash	6f9216d544	A64: Implement RBIT	2020-04-22 20:44:37 +01:00
MerryMage	d4b05b28cf	A64: Implement CLS ... This is not the cleanest implementation.	2020-04-22 20:42:46 +01:00
MerryMage	b8e26bfdc3	A64: Implement ADDP (vector)	2020-04-22 20:42:46 +01:00
Lioncash	bb1c5bd3b2	A64: Implement SMADDL, SMSUBL, UMADDL, and UMSUBL	2020-04-22 20:42:46 +01:00
Lioncash	c1a25bfc2f	A64: Implement MADD and MSUB	2020-04-22 20:42:46 +01:00
Lioncash	b7c5055d42	A64: Implement CLZ	2020-04-22 20:42:46 +01:00
Lioncash	ae5dbcbed6	A64: Implement HINT, NOP, YIELD, WFE, WFI, SEV, and SEVL ... Truly the most difficult A64 instructions to implement.	2020-04-22 20:42:46 +01:00
Lioncash	4d8f4aa8af	A64: Implement ASRV, LSLV, LSRV, and RORV	2020-04-22 20:42:46 +01:00
Lioncash	a8a65beb2b	data_processsing_conditional_select: Implement CSINC, CSINV and CSNEG	2020-04-22 20:42:46 +01:00
MerryMage	f81d0a2536	A64: Implement AND (vector)	2020-04-22 20:42:46 +01:00
MerryMage	a63fc6c89b	A64: Implement ADD (vector, vector)	2020-04-22 20:42:46 +01:00
Thomas Guillemard	896cf44f96	A64: Implement REV, REV32, and REV16 (#126)	2020-04-22 20:42:46 +01:00
MerryMage	144b629d8a	A64: Implement CSEL	2020-04-22 20:42:45 +01:00
MerryMage	9f57283a30	A64: Implement SBFM, BFM, UBFM	2020-04-22 20:42:45 +01:00
MerryMage	cdbc8d07a5	A64: Implement MOVN, MOVZ, MOVK	2020-04-22 20:42:45 +01:00
MerryMage	b34c6616d4	A64/decoder: Split decoder data from header	2020-04-22 20:42:45 +01:00