MerryMage
a8a712c801
Relicense to 0BSD
2020-04-23 15:45:57 +01:00
Lioncash
9365487797
frontend/A32/ir_emitter: Remove unnecessary includes
...
std::initializer_list isn't used anywhere in here, and we can just
forward declare the CoprocReg enum to avoid needing to include the
header.
2020-04-22 21:04:22 +01:00
Lioncash
bd755ae494
frontend/ir/ir_emitter: Add A32 equivalent to A64's SetCheckBit
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This will be used in a subsequent change to implement ARMv6T2's CBZ/CBNZ
Thumb-1 instructions.
2020-04-22 21:02:47 +01:00
Lioncash
196e7b5e35
frontend/A32/ir_emitter: Mark locals as const where applicable
...
Makes const usage consistent within the source file.
2020-04-22 21:02:46 +01:00
Lioncash
8316d231e9
A32: Implement barrier instructions introduced in ARMv7
...
Provides basic implementations of the barrier instruction introduced
within ARMv7. Currently these simply mirror the behavior of the AArch64
equivalents.
2020-04-22 21:02:46 +01:00
Lioncash
ee973f13c7
frontend/A32/ir_emitter: Mark PC() and AlignPC() as const-qualified member functions
...
These don't modify instance state, so they can be const-qualified member
functions.
2020-04-22 20:57:38 +01:00
MerryMage
2524d536b0
A32/ir_emitter: Bugfix: ExceptionRaised was producing incorrect PC
...
Use actual PC and not pipelined PC.
2020-04-22 20:56:01 +01:00
Lioncash
2188765e28
ir/value: Use type alias CoprocessorInfo for std::array<u8, 8>
...
Provides a more descriptive label for the interface, and avoids the need
to hardcode the array size in multiple places.
2020-04-22 20:46:23 +01:00
MerryMage
5fc197c564
A32/ir_emitter: Bug fix: IREmitter::ExceptionRaised using incorrect opcode
2020-04-22 20:46:23 +01:00
MerryMage
aac5af50e2
IR: FPCompare{32,64} now return NZCV flags instead of implicitly setting them
2020-04-22 20:46:13 +01:00
MerryMage
f023bbb893
A32: Add ExceptionRaised IR instruction and use it
2020-04-22 20:46:12 +01:00
Lioncash
67443efb62
General: Convert multiple namespace specifiers to nested namespace specifiers where applicable
...
Makes namespacing a little less noisy
2020-04-22 20:44:38 +01:00
MerryMage
5eb0bdecdf
IR: Simplify types. F32 -> U32, F64 -> U64, F128 -> U128
...
ARM's Architecture Specification Language doesn't distinguish between floats and integers
as much as we do. This makes some things difficult to implement. Since our register
allocator is now capable of allocating values to XMMs and GPRs as necessary, the
Transfer IR instructions are no longer necessary as they used to be and they can be
removed.
2020-04-22 20:42:46 +01:00
MerryMage
f61da0b5a9
IR: Compile-time type-checking of IR
2020-04-22 20:39:27 +01:00
MerryMage
8bef20c24d
IR: Split off A32 specific opcodes
2020-04-22 20:33:32 +01:00
MerryMage
b1f0cf9278
A32: Split off A32 specific IREmitter
2020-04-22 20:33:32 +01:00
