18 Commits

Author	SHA1	Message	Date
MerryMage	aed4fd3ec3	A64: Implement FADD (vector), vector variant	2020-04-22 20:46:14 +01:00
MerryMage	f1cb5581c9	A64: Implement FSUB (vector)	2020-04-22 20:46:14 +01:00
MerryMage	1dd2b33b87	A64: Implement MLS (vector)	2020-04-22 20:46:14 +01:00
MerryMage	5eac3abf52	A64: Implement MLA (vector)	2020-04-22 20:46:14 +01:00
MerryMage	3afd2fcbad	A64: Implement MUL (vector)	2020-04-22 20:46:14 +01:00
MerryMage	faeb77e8c4	A64: Implement SUB (vector)	2020-04-22 20:46:14 +01:00
MerryMage	d3a4e1efe2	IR: Vector instructions now take esize argument in emitter	2020-04-22 20:46:13 +01:00
MerryMage	15e8231f24	opcodes: Sort vector IR opcodes alphabetically	2020-04-22 20:46:13 +01:00
FernandoS27	15871910af	Implemented BSL, BIC, BIT and BIF vector instructions	2020-04-22 20:46:13 +01:00
MerryMage	2a0850c068	A64: Reorganize decoder tables (some vector entries were grouped with scalar entries)	2020-04-22 20:46:13 +01:00
MerryMage	7b33772ac6	A64: Implement BIC (vector, register)	2020-04-22 20:46:13 +01:00
Lioncash	67443efb62	General: Convert multiple namespace specifiers to nested namespace specifiers where applicable ... Makes namespacing a little less noisy	2020-04-22 20:44:38 +01:00
Lioncash	7abd673a49	A64: Zero upper 64 bits in ORN if using the 64-bit variant ... Resolves a TODO	2020-04-22 20:44:38 +01:00
MerryMage	75756137c6	A64: Implement CMEQ (register, vector)	2020-04-22 20:44:38 +01:00
Fernando Sahmkow	e0c12ec2ad	A64: Implemented EOR (vector), ORR (vector, register) and ORN (vector) Instructions (#142)	2020-04-22 20:44:38 +01:00
MerryMage	b8e26bfdc3	A64: Implement ADDP (vector)	2020-04-22 20:42:46 +01:00
MerryMage	f81d0a2536	A64: Implement AND (vector)	2020-04-22 20:42:46 +01:00
MerryMage	a63fc6c89b	A64: Implement ADD (vector, vector)	2020-04-22 20:42:46 +01:00