63 Commits

Author SHA1 Message Date
Markus Wick
b2acdec8cb backend/x64: Fix PerfMapRegister usages.
Both the far code and fast_dispatch_table_lookup were missing.
2021-04-02 00:17:07 +02:00
MerryMage
62003a2d89 A32/ir_emitter: Implement UpdateUpperLocationDescriptor 2021-02-07 20:41:48 +00:00
MerryMage
f229a68aed a32_emit_x64: Update upper_location_descriptor in BXWritePC based on final location 2021-02-07 20:41:48 +00:00
bunnei
de389968eb A32: Add hook_isb option. 2021-01-28 20:47:39 -08:00
ReinUsesLisp
4a9a0d07f7 backend/{a32,a64}_emit_x64: Add config entry to mask page table pointers
Add config entry to mask out the lower bits in page table pointers.
This is intended to allow users of Dynarmic to pack small integers
inside pointers and update the pair atomically without locks.
These lower bits can be masked out due to the expected alignment in
pointers inside the page table.

For the given usage, using AND on the pointer acts the same way as a
TEST instruction. That said when the mask value is zero, TEST is still
emitted to keep the same behavior.
2020-12-29 19:16:46 +00:00
MerryMage
4ba1f8b9e7 Add optimization flags to disable specific optimizations 2020-07-04 11:04:10 +01:00
MerryMage
656419286c ir: Add fpcr_controlled argument to FPVector{Equal,Greater,GreaterEqual} 2020-06-20 00:50:40 +01:00
MerryMage
b759773b3b a32_emit_x64: EmitVAddrLookup: Use 64-bit registers where required 2020-06-19 00:44:52 +01:00
MerryMage
7dd9901de2 a32_emit_x64: Incorrect type in ExclusiveWriteMemory 2020-06-19 00:19:46 +01:00
MerryMage
13367a7efd A64: Match A32 page_table code
Here we increase the similarity between the A64 and A32 front-ends in terms of their
page_table handling code. In this commit, we:

* Reserve and use r14 as a register to store the page_table pointer.
* Align the code to be more similar in structure.
* Add a conf member to A32EmitContext.
* Remove scratch argument from EmitVAddrLookup.
2020-06-18 12:22:59 +01:00
MerryMage
b88c291f81 A32: Detect misaligned memory accesses
This avoids issues with misaligned memory accesses writing into the next page.
2020-06-17 17:51:37 +01:00
MerryMage
9f3277540a Merge A32 and A64 exclusive monitors 2020-06-17 10:33:09 +01:00
MerryMage
2c1a4843ad A32 global exlcusive monitor 2020-06-16 17:54:21 +01:00
MerryMage
58abdcce5b backend/x64/a32_*: Rename config to conf
Standardize on one name for both a32_* and a64_*.
2020-06-16 14:56:44 +01:00
MerryMage
7ea521b8bf a32_emit_x64: Change ExclusiveWriteMemory64 to require a single U64 argument 2020-06-16 13:32:50 +01:00
MerryMage
aa341b7eea a32_emit_x64: Make ExclusiveWrite a member function of A32EmitX64 2020-06-16 13:03:17 +01:00
MerryMage
34ef5142e3 a32_emit_x64: Specify callback as template argument
Removes unnecessary switch statement.
2020-06-16 10:23:51 +01:00
MerryMage
58b2c83944 a32_emit_x64: Reduce mov code duplication in {Read,Write}Memory 2020-06-16 10:14:06 +01:00
MerryMage
55bddc767f backend/x64: Touch PEXT/PDEP code
* Use pext/pdep where not previously used
* Limit pext/pdep to non-AMD platforms due to slowness on AMD
* Use imul/and as alternatives for AMD and non-BMI2 platforms
2020-06-10 22:30:22 +01:00
MerryMage
f495018f53 block_of_code: Encapsulate CPU feature detection code 2020-06-09 21:25:57 +01:00
MerryMage
07108246cf A32/IR: Add SetVector and GetVector 2020-05-28 20:39:19 +01:00
MerryMage
93c289b54f Use tsl::robin_map and tsl::robin_set
Replace std::unordered_map and std::unordered_set with the above.
Better performance profile.
2020-05-26 20:51:48 +01:00
MerryMage
8b3bc92bce backend/x64: Reduce conversions required for cpsr_nzcv
The guest program often accesses the NZCV flags directly much less
often than we need to use them for jumps and other such uses.

Therefore, we store our flags in cpsr_nzcv in a x64-friendly format.

This allows for a reduction in conditional jump related code.
2020-05-06 22:38:06 +01:00
MerryMage
94d0d33e02 Fix single stepping for certain instructions
Several issues:
1. Several terminal instructions did not stop at the end of a single-step block
2. x64 backend for the A32 frontend sometimes polluted upper_location_descriptor with the single-stepping flag

We also introduce the enable_optimizations parameter to the A32 frontend.
2020-04-24 11:44:38 +01:00
MerryMage
a8a712c801 Relicense to 0BSD 2020-04-23 15:45:57 +01:00
MerryMage
cd1560c664 emit_x64: Do not clear fast_dispatch_table unnecessarily
Reduces invalidation overhead
2020-04-22 21:06:18 +01:00
MerryMage
4636055646 a32_emit_x64: Implement fastmem 2020-04-22 21:06:17 +01:00
MerryMage
f9b9081d4c a32_emit_x64: Fully wrapped memory fallbacks
In the same style as the A64 backend
2020-04-22 21:06:17 +01:00
MerryMage
ad52c997f4 a32_emit_x64: Use r14 for page_table pointer 2020-04-22 21:06:17 +01:00
MerryMage
49fcfe040c reg_alloc: Explicitly specify GPR and XMM order
This allows each backend to modify what registers they want to use and their preferred orderings
2020-04-22 21:06:17 +01:00
MerryMage
c232ad7971 a32_emit_x64: Make {Read,Write}Memory member functions of A32EmitX64 2020-04-22 21:06:17 +01:00
MerryMage
325808949f backend/x64: Rename namespace BackendX64 -> Backend::X64 2020-04-22 21:06:17 +01:00
MerryMage
bd88286b21 cast_util: Add FptrCast
Reduce unnecessary type duplication when casting a lambda to a function pointer.
2020-04-22 21:06:17 +01:00
Marshall Mohror
1ebc1895ee A32/x64: Create a global_offset optimization for the page table (#507)
Instead of looking up the page table like:
  table[addr >> 12][addr & 0xFFF]
We can use a global offset on the table to query the memory like:
  table[addr >> 12][addr]

This saves two instructions on *every* memory access within the recompiler.

Original change by degasus in A64 emitter
2020-04-22 21:04:23 +01:00
MerryMage
6325ac23eb a32_emit_x64: Use std::get_if in EmitA32Coproc* 2020-04-22 21:04:23 +01:00
MerryMage
c7d20f3f2f fuzz_arm: Test MSR and MRS instructions against unicorn
* Add always_little_endian option to mach unicorn behavior.
* Correct CPSR.Mode = Usermode
2020-04-22 21:04:23 +01:00
MerryMage
2f06ef5d4e a32_emit_x64: EmitA32SetCpsr: BUGFIX: Actually set CPSR.GE
Was unintentionally masking the writing of CPSR.GE due to 32-bit immediate sign extension.
2020-04-22 21:04:23 +01:00
MerryMage
0a6f822d76 a32_emit_x64: GenTerminalHandlers: Remove unnecessary mov 2020-04-22 21:04:23 +01:00
MerryMage
2f2a859615 a32_jitstate: Consolidate upper bits of location descriptor into upper_location_descriptor
Also solves a performance regression initially introduced by b6e8297e369f2dc4758bafe944e51efb8d1a2552,
primarily due to excessively mismatched load/store sizes causing less than optimal load-to-store forwarding.
2020-04-22 21:04:23 +01:00
Merry
f252a62c1b Merge pull request #502 from lioncash/header
General: Remove unnecessary includes
2020-04-22 21:04:22 +01:00
Lioncash
349d4b577a General: Remove unnecessary includes
Removes unnecessary header dependencies that have accumulated over time
as changes have been made. Lessens the amount of files that need to be
rebuilt when the headers change.
2020-04-22 21:04:22 +01:00
Lioncash
6b9bf7868a General: Correct typos is code comments 2020-04-22 21:04:22 +01:00
MerryMage
5f8eb7c51c A32/location_descriptor: Add CPSR.IT to A32::LocationDescriptor 2020-04-22 21:04:22 +01:00
MerryMage
6e2cd35e4f a32_jitstate: Optimize runtime location descriptor calculation
Calculation is now one unaligned 64-bit load.
2020-04-22 21:04:22 +01:00
MerryMage
6f49c0ef8e {a32,a64}_jitstate: Rename CPSR_* to cpsr_* 2020-04-22 21:04:22 +01:00
MerryMage
b3bb544bca a32_jitstate: Rename FPSCR_nzcv to fpsr_nzcv 2020-04-22 21:04:22 +01:00
MerryMage
76f986979d a32_jitstate: Rename FPSCR_mode to fpcr_mode 2020-04-22 21:04:22 +01:00
Merry
fd6222f0a1 Merge pull request #500 from lioncash/cbz
A32: Implement Thumb-1's CBZ/CBNZ instructions
2020-04-22 21:04:21 +01:00
Lioncash
bd755ae494 frontend/ir/ir_emitter: Add A32 equivalent to A64's SetCheckBit
This will be used in a subsequent change to implement ARMv6T2's CBZ/CBNZ
Thumb-1 instructions.
2020-04-22 21:02:47 +01:00
Lioncash
92daae9513 A32/coprocessor: Remove boost from public interface
Removes a boost header from the public includes in favor of using the
standard-provided std::variant.

The use of boost in public interfaces is often a dealbreaker for some
people. Given we use std::optional in the header already, we can
transition over to std::variant from boost::variant.

With this removal, this makes all of our dependencies internal to the
library itself.
2020-04-22 21:02:47 +01:00