MerryMage
4df3b2f97f
vfp: Add decoders for VFPv5
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These instructions were introduced in the Cortex-M7
2020-06-19 19:24:32 +01:00
Lioncash
551e207661
A32: Implement ASIMD VSUB (integer)
2020-06-19 11:31:38 +01:00
Lioncash
4d6f68525d
A32: Implement ASIMD VADD (integer)
2020-06-19 11:31:38 +01:00
Lioncash
fbdae61c13
A32: Implement ASIMD VMVN (register)
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Fairly straightforward
2020-06-19 11:31:14 +01:00
merry
687c604197
Merge pull request #532 from lioncash/shift
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A32: Implement several ASIMD shift instructions
2020-06-19 00:22:18 +01:00
Lioncash
00b2f9b319
asimd: Prevent misdecodes from occurring
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Pointed out by Mary when reviewing the shift code.
2020-06-18 15:04:48 -04:00
MerryMage
d34763242c
Revert "A32: Implement ASIMD VCEQ, VCGE, VCGT, VCLE, VCLT with zero"
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This reverts commit 179951b10f6f7eb7b608574703ec8fe46bf5f63f.
These instructions require StandardFPSCRValue.
2020-06-18 17:38:40 +01:00
Lioncash
179951b10f
A32: Implement ASIMD VCEQ, VCGE, VCGT, VCLE, VCLT with zero
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Fairly self-explanatory, we can leverage the existing IR functions for
the purpose of these instructions.
In the integer case, we can just insert function pointers
into an array and index it, given all comparison primitives exist
already for the integer side of things.
2020-06-18 17:01:57 +01:00
Lioncash
6ca20c2fe3
A32: Implement ASIMD VSLI
2020-06-18 11:51:08 -04:00
Lioncash
887732d8a8
A32: Implement ASIMD VSRI
2020-06-18 11:28:12 -04:00
Lioncash
8b98c91ecc
A32: Implement ASIMD VSHL
2020-06-18 11:18:33 -04:00
Lioncash
69c999bc66
A32: Implement ASIMD VRSRA
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Now that we have the accumulation and rounding code in place, VRSRA is
extremely trivial to implement.
2020-06-18 11:03:39 -04:00
Lioncash
14fdd15199
A32: Implement ASIMD VRSHR
2020-06-18 11:00:45 -04:00
Lioncash
276e0b71dc
A32: Implement ASIMD VSRA
2020-06-18 11:00:27 -04:00
Lioncash
054dff7cd5
A32: Implement ASIMD VTST
2020-06-18 15:34:05 +01:00
Lioncash
6c142bc5cc
A32: Implement ASIMD VSHR
2020-06-18 10:30:20 -04:00
Lioncash
08350d06f1
A32: Implement ASIMD VQNEG
2020-06-18 09:49:29 +01:00
Lioncash
f6b665f5a4
A32: Implement ASIMD VQABS
2020-06-18 09:49:29 +01:00
Lioncash
4b371c0445
A32: Implement ASIMD VREV{16, 32, 64}
2020-06-17 10:21:59 +01:00
Lioncash
6dd2c94095
A32: Implement ASIMD VABS
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Very similar to VNEG in that the only thing that differs is the function
called.
2020-06-16 22:42:18 +01:00
Lioncash
93ed3441b7
A32: Implement ASIMD VCLS/VCLZ/VCNT
2020-06-16 09:54:28 +01:00
Lioncash
15b3de95e4
A32: Implement VNEG
2020-06-16 01:53:21 +01:00
MerryMage
f3845cea9a
A32: Implement ASIMD VQSUB instruction
2020-05-30 18:19:17 +01:00
MerryMage
16ff880f8f
A32: Implement ASIMD VQADD
2020-05-30 16:09:37 +01:00
MerryMage
3a50d444dc
A32: Implement ASIMD VHSUB
2020-05-28 22:29:00 +01:00
MerryMage
205e6c5a56
A32: Implement ASIMD VRHADD
2020-05-28 22:29:00 +01:00
MerryMage
946eb03a3b
A32: Implement ASIMD VHADD
2020-05-28 22:29:00 +01:00
Lioncash
fc112e61f2
A32: Implement ASIMD modified immediate functions
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Implements VBIC, VMOV, VMVN, and VORR modified immediate instructions.
2020-05-24 23:55:47 +01:00
Lioncash
659d78c9c4
A32: Implement ASIMD VSWP
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A trivial one to implement, this just swaps the contents of two
registers in place.
2020-05-22 19:43:24 +01:00
MerryMage
d0b45f6150
A32: Implement ARMv8 VST{1-4} (multiple)
2020-05-17 17:01:39 +01:00
Lioncash
f42b3ad4a0
A32: Implement ASIMD VBIF (register)
2020-05-16 20:22:12 +01:00
Lioncash
ee9a81dcba
A32: Implement ASIMD VBIT (register)
2020-05-16 20:22:12 +01:00
Lioncash
d624059ead
A32: Implement ASIMD VBSL (register)
2020-05-16 20:22:12 +01:00
Lioncash
4b5e3437cf
A32: Implement ASIMD VEOR (register)
2020-05-16 20:22:12 +01:00
Lioncash
67b284f6fa
A32: Implement ASIMD VORN (register)
2020-05-16 20:22:12 +01:00
Lioncash
1fdd90ca2a
A32: Implement ASIMD VORR (register)
2020-05-16 20:22:12 +01:00
Lioncash
64fa804dd4
A32: Implement ASIMD VBIC (register)
2020-05-16 20:22:12 +01:00
Lioncash
0441ab81a1
A32: Implement ASIMD VAND (register)
2020-05-16 20:22:12 +01:00
MerryMage
1a0bc5ba91
A32/ASIMD: ARMv8: Implement VLD{1-4} (multiple)
2020-05-16 14:11:23 +01:00
MerryMage
e7f1a0d408
A32: ARMv8: Implement LDA{,EX}{,B,D,H} and STL{,EX}{,B,D,H}
2020-05-15 21:07:36 +01:00
MerryMage
59db2c191a
VFPv3: Implement VMOV (immediate)
2020-05-10 15:09:37 +01:00
MerryMage
3c86d58064
VFPv4: Implement VCVTB, VCVTT
2020-05-10 14:45:18 +01:00
MerryMage
010fab9a0e
VFPv4: Implement VFMA, VFMS
2020-05-10 14:20:11 +01:00
MerryMage
8e97b10acb
VFPv4: Implement VFNMS, VFNMA
2020-05-10 14:14:03 +01:00
MerryMage
6df660c889
fuzz_arm: Ensure all instructions are fuzzed
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* VFP instructions were not getting fuzzed due to matching coprocessor instructions (as invalid instructions)
* Fix VPOP writeback for doubles when (imm8 & 1) == 1
* Do not accidentally fuzz unimplemented unconditional instructions
2020-05-10 13:57:39 +01:00
MerryMage
9a38c7324f
A32: Add decoders for remaining v7 instructions
2020-05-10 10:50:34 +01:00
MerryMage
a8a712c801
Relicense to 0BSD
2020-04-23 15:45:57 +01:00
Merry
fd6222f0a1
Merge pull request #500 from lioncash/cbz
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A32: Implement Thumb-1's CBZ/CBNZ instructions
2020-04-22 21:04:21 +01:00
Lioncash
03e6899fd7
A32: Implement Thumb-1's CBZ/CBNZ instructions
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Introduced in ARMv6T2, this allows for short forward branches.
2020-04-22 21:02:47 +01:00
Lioncash
106c8c2473
A32: Implement ARM-mode MOVW
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Introduced to the ISA in ARMv6T2
2020-04-22 21:02:47 +01:00
