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Commit Graph

1495 Commits

Author SHA1 Message Date
MerryMage
c6ecc835b6 ASIMD: Implement VCVT (between half-precision and single-precision) 2021-05-16 23:48:29 +01:00
MerryMage
b6bff56523 translate_thumb: Update current_instruction_size in TranslateSingleThumbInstruction 2021-05-16 10:31:30 +01:00
MerryMage
1643e8f3c6 translate_thumb: VFP/ASIMD conflict with coprocessor instructions 2021-05-15 20:54:35 +01:00
MerryMage
b93ae62acf thumb32: Add coprocessor instructions 2021-05-13 18:15:35 +01:00
MerryMage
05a6b5f623 translate_thumb: Permit ASIMD element or structure load/store instructions to be translated 2021-05-07 12:47:55 +01:00
sunho
cb79bfa1dc thumb32: Support setflags in shift reg instructions 2021-05-05 11:47:49 +01:00
MerryMage
075fdeaee0 thumb32: Add Rn argument to ADD/SUB (Plain Binary Immediate) 2021-05-05 11:47:49 +01:00
MerryMage
462c884685 frontend/A32: Correct more IT state 2021-05-04 16:25:24 +01:00
MerryMage
c5f5c1d40f frontend: Standardize emitted IR for exception raising 2021-05-04 16:14:26 +01:00
MerryMage
f8d8ea0deb thumb32: Implement MRS (register) 2021-05-04 12:43:51 +01:00
MerryMage
61333917a4 thumb32: Implement MRS (register) 2021-05-04 12:43:38 +01:00
MerryMage
a5a210a9a5 T32: Add ASIMD instructions 2021-05-04 00:09:55 +01:00
MerryMage
d1e62b9993 T32: Add VFP instructions 2021-05-04 00:09:55 +01:00
MerryMage
cd837c5b37 A32: Merge ArmTranslateVistor and ThumbTranslateVisitor 2021-05-04 00:09:55 +01:00
MerryMage
6d292e3eac decoder: Ensure more compiler-time computation 
Replace with consteval when C++20 hits
 2021-05-03 13:09:51 +01:00
MerryMage
e19f898aa2 ir: Reorganize to new top level folder 2021-04-21 22:22:07 +01:00
Lioncash
f5263cc196 thumb32: Implement exclusive loads 
Implements the remaining loads for ARMv7
 2021-04-19 19:46:19 +01:00
MerryMage
9c6332fcbd thumb32_load_store_dual: imm8 in STREX should be shifted left by 2 2021-04-19 18:57:28 +01:00
Lioncash
6241ff6be2 thumb32: Implement STREX variants 
Implements the exclusive store instructions. Now all that remains for
ARMv7 load/stores to be done is the exclusive loads.
 2021-04-10 17:15:19 +01:00
MerryMage
d8066b091b decoder/arm: Complete instruction version information 2021-04-10 17:11:24 +01:00
Lioncash
5873e6b955 thumb32: Implement LDRD (immediate) 2021-03-13 15:29:56 -05:00
Lioncash
9757e2353f thumb32: Implement LDRD (literal) 2021-03-13 15:29:56 -05:00
Lioncash
a74843ca17 thumb32: Implement STRD 2021-03-13 15:29:56 -05:00
Lioncash
258ca93c53 thumb32: Implement TBB/TBH 2021-03-13 15:29:49 -05:00
Lioncash
1d0b705996 thumb32: Implement PUSH 
This can be handled as an alias for STMDB.
 2021-03-12 19:54:35 -05:00
Lioncash
9cb4790428 thumb32: Implement POP 
This can just be treated as an alias to LDMIA
 2021-03-12 19:43:47 -05:00
Lioncash
39edee70ff thumb32: Implement LDMDB/LDMEA 2021-03-12 19:35:28 -05:00
Lioncash
ae83713f4f thumb32: Simplify existing store functions into helper function 
We can also make a STM helper.
 2021-03-12 19:30:29 -05:00
Lioncash
0d887d9ecd thumb32: Implement LDMIA/LDMFD 2021-03-12 19:26:03 -05:00
Lioncash
714ccf13dd thumb32: Implement STMDB/STMFD 2021-03-12 19:05:39 -05:00
Lioncash
91c4d59da9 thumb32: Implement STMIA/STMEA 2021-03-12 19:05:15 -05:00
merry
543ba4e61f
Merge pull request #589 from lioncash/adr 
thumb32: Implement plain binary immediate ADR variants
 2021-03-12 23:10:23 +00:00
Lioncash
85b8adeb32 thumb32: Implement plain binary immediate ADR variants 
Now all the plain binary immediate instructions are implemented.
 2021-03-12 18:05:41 -05:00
Lioncash
bd02d9e27f thumb32: Implement STR immediate variants 2021-03-12 14:03:40 -05:00
Lioncash
2521314384 thumb32: Implement STRH immediate variants 2021-03-12 13:55:39 -05:00
Lioncash
cbf9027278 thumb32: Implement STRB immediate variants 2021-03-12 13:33:11 -05:00
merry
2093d2b775
Merge pull request #587 from lioncash/8dot7 
a64: Add v8.7 instruction additions to the decoder
 2021-03-10 21:19:03 +00:00
Lioncash
035580abd2 a64: Add v8.7 instruction additions to the decoder 
Adds the instructions introduced in FEAT_WFxT and FEAT_LS64/FEAT_LS64_V
in ARMv8.7
 2021-03-09 18:41:20 -05:00
Lioncash
fb30922cd1 thumb32: Add supporting decoder entry for PLD (literal) 
LDRH (literal)'s pseduocode indicates that cases where Rt specifies the
PC, that the instruction should be execured as if it were a PLD
instruction.

Curiously, however, within the ARM reference manual, the encodings in the case
that happens doesn't match up.

The bit pattern for LDRH (literal) has bit 21 set to 1, but the encoding
of PLD (literal) has bit 21 set to zero for it's only thumb encoding.
 2021-03-09 18:16:08 -05:00
Lioncash
921998f6e9 thumb32: Implement LDRSH variants 2021-03-09 18:11:33 -05:00
Lioncash
7a9bdc8f21 thumb32: Implement LDRH variants 2021-03-09 17:12:46 -05:00
Lioncash
3d7e81e7d1 thumb32: Implement LDR variants 2021-03-09 13:12:15 -05:00
MerryMage
646fd05920 thumb32: Implement RSB (reg) 2021-03-06 19:49:44 +00:00
MerryMage
3f97cb1f9b thumb32: Implement SUB (reg) 2021-03-06 19:49:44 +00:00
MerryMage
17bdb54d30 thumb32: Implement CMP (reg) 2021-03-06 19:49:44 +00:00
MerryMage
a63271fd3b thumb32: Implement SBC (reg) 2021-03-06 19:49:44 +00:00
MerryMage
95189b78ef thumb32: Implement ADC (reg) 2021-03-06 19:49:44 +00:00
MerryMage
af33155ef8 thumb32: Implement ADD (reg) 2021-03-06 19:49:44 +00:00
MerryMage
41ac9971f4 thumb32: Implement CMN (reg) 2021-03-06 19:49:44 +00:00
MerryMage
e7ecd3a7ee thumb32: Implement PKHBT, PKHTB 2021-03-06 19:49:44 +00:00