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9 Commits

Author SHA1 Message Date
bunnei
caab1bbc7c arm: Implement STR reg/imm instructions. 2016-08-05 20:04:56 -04:00
bunnei
b09ecb4532 arm: Implement LDR reg/imm instructions. 2016-08-05 20:04:55 -04:00
Tillmann Karras
fce8c86c90 Implement RSB 
somehow missed this earlier
 2016-08-05 02:13:26 +01:00
Tillmann Karras
eb2e6e8bea Implement some multiplies 2016-08-05 02:09:54 +01:00
bunnei
691e4139fa arm: Implement B/BL/BX instructions. 2016-08-03 16:49:01 -04:00
Tillmann Karras
fc33f1d374 Implement more instructions 
SXTB, SXTH, SXTAB, SXTAH, UXTB, UXTH, UXTAB, UXTAH, REV16
 2016-08-03 00:47:17 +01:00
Tillmann Karras
30a90295b9 Implement data processing instructions 
ADC, ADD, AND, BIC, CMN, CMP, EOR, MOV, MVN, ORR, RSB, RSC, SBC, SUB,
TEQ, TST

The code could use some serious deduplication...
 2016-08-03 00:47:16 +01:00
MerryMage
a875c0c720 TranslateArm: Stub more ARM instructions 2016-08-02 21:59:33 +01:00
MerryMage
6097a21955 TranslateArm: Reorganisation - Split visitor into multiple .cpp files 2016-08-02 11:54:04 +01:00