456 Commits

Author SHA1 Message Date
MerryMage
6e2cd35e4f a32_jitstate: Optimize runtime location descriptor calculation
Calculation is now one unaligned 64-bit load.
2020-04-22 21:04:22 +01:00
MerryMage
f178562ee7 a32_jitstate: Remove exception trap enables from FPSCR_MODE_MASK
We don't currently use this for anything (we do not currently trap
floating point exceptions).

This frees these bits up for other purposes.
2020-04-22 21:04:21 +01:00
Merry
fd6222f0a1 Merge pull request #500 from lioncash/cbz
A32: Implement Thumb-1's CBZ/CBNZ instructions
2020-04-22 21:04:21 +01:00
Merry
bab4e29075 Merge pull request #498 from lioncash/ahp
A32/location_descriptor: Add AHP bit to the FPSCR mask
2020-04-22 21:04:21 +01:00
Lioncash
87083af733 general: Remove trailing spaces
General code-related cleanup. Gets rid of trailing spaces in the
codebase.
2020-04-22 21:04:21 +01:00
Lioncash
03e6899fd7 A32: Implement Thumb-1's CBZ/CBNZ instructions
Introduced in ARMv6T2, this allows for short forward branches.
2020-04-22 21:02:47 +01:00
Lioncash
d02a4e6fc9 A32/location_descriptor: Add AHP bit to the FPSCR mask
Ensures the alternate half-precision state is preserved within the
location descriptors, which will be necessary when implementing the
half-precision extensions for VFP and NEON.
2020-04-22 21:02:47 +01:00
Lioncash
bd755ae494 frontend/ir/ir_emitter: Add A32 equivalent to A64's SetCheckBit
This will be used in a subsequent change to implement ARMv6T2's CBZ/CBNZ
Thumb-1 instructions.
2020-04-22 21:02:47 +01:00
Lioncash
106c8c2473 A32: Implement ARM-mode MOVW
Introduced to the ISA in ARMv6T2
2020-04-22 21:02:47 +01:00
Lioncash
9935f3aa28 A32: Implement Thumb-1 variant of SEVL
While we're at it, also add the Thumb-2 encoding to the encoding table
to make sure it isn't forgotten about in the future.
2020-04-22 21:02:47 +01:00
Lioncash
9a097e307f A32: Implement the ARM-mode variant of SEVL 2020-04-22 21:02:47 +01:00
Lioncash
e89ca42048 A32: Implement Thumb-1 variant of YIELD 2020-04-22 21:02:47 +01:00
Lioncash
ebab7ede55 A32: Implement Thumb-1 variant of WFI 2020-04-22 21:02:47 +01:00
Lioncash
b4110af22a A32: Implement Thumb-1 variant of WFE 2020-04-22 21:02:47 +01:00
Lioncash
57675fe592 A32: Implement Thumb-1 variant of SEV 2020-04-22 21:02:47 +01:00
Lioncash
07699b47ba A32/translate_thumb: Add helper function for raising exceptions
Similar to the variant within the ARM-mode translator visitor. This will
be used in subsequent changes to implement the hint instructions
introduced in ARMv7.
2020-04-22 21:02:47 +01:00
Lioncash
64879396f6 A32: Implement Thumb-1 variant of NOP 2020-04-22 21:02:47 +01:00
Merry
81b908b077 Merge pull request #495 from lioncash/bkpt
A32: Implement Thumb-16's variant of BKPT
2020-04-22 21:02:47 +01:00
Merry
30d28029a8 Merge pull request #492 from lioncash/vfp
A32: Rename vfp2-related files to vfp
2020-04-22 21:02:47 +01:00
Lioncash
b17a5d3365 A32: Implement Thumb-16's variant of BKPT 2020-04-22 21:02:47 +01:00
Lioncash
b902f72001 A32/disassembler_arm: Remove <unimplemented> from hint instruction output
Given we now support hooking these hint instructions, we can consider
them implemented.
2020-04-22 21:02:47 +01:00
Lioncash
0fa0bca22a A32: Handle different variants of PLD 2020-04-22 21:02:47 +01:00
Merry
9ba503e394 Merge pull request #491 from lioncash/hint
A32: Allow hooking of hint instructions in ARM mode.
2020-04-22 21:02:46 +01:00
Lioncash
97277c598b A32: Rename vfp2-related files to vfp
Now that we fuzz against Unicorn, we aren't just restricted to VFPv2.
VFPv3 and VFPv4 facilities can now be implemented. This renames
constructs mentioning VFPv2 to just refer to VFP.
2020-04-22 21:02:46 +01:00
Lioncash
966e04d03d A32: Allow hooking of hint instructions in ARM mode.
Mirrors the hooking functionality from the AArch64 frontend to make the
behavior of both consistent.
2020-04-22 21:02:46 +01:00
Lioncash
e37689315d A32: Implement ARM-mode CRC32 instructions
Implements the ARM-mode variants of the CRC32 instructions introduced
within ARMv8. This is also one of the instruction cases where there is
UNPREDICTABLE behavior that is constrained (we must do one of the
options indicated by the reference manual).

In both documented cases of constrained unpredictable behavior, we treat
the instructions as unpredictable in order to allow library users to
hook the unpredictable exception to provide the intended behavior they
desire.
2020-04-22 21:02:46 +01:00
Lioncash
95d9baea67 {A32, A64}/types: Use std::array deduction guides where applicable
We also make the arrays static here, as MSVC tends to load the whole
array every time the function is called, instead of storing the data
within rodata.

This also line breaks the elements a little earlier for readability.
2020-04-22 21:02:46 +01:00
Lioncash
bac945f2d8 A32: Resolve parameter discrepancies discovered via use of the Imm template 2020-04-22 21:02:46 +01:00
Lioncash
4ba2318b2e A32: Replace immediate type aliases with the Imm template
Replaces type aliases of raw integral types with the more type-safe Imm
template, like how the AArch64 frontend has been using it.

This makes the two frontends more consistent with one another.
2020-04-22 21:02:46 +01:00
Lioncash
f96036b3f1 A32/barrier: Correct PC assignment within ISB
The SetRegister() IR function doesn't allow specifying the PC as a
register. This is a discrepancy that slipped through (my bad). Instead,
we can use BranchWritePC(), like how the other similar PC modifying
locations do it.
2020-04-22 21:02:46 +01:00
Lioncash
196e7b5e35 frontend/A32/ir_emitter: Mark locals as const where applicable
Makes const usage consistent within the source file.
2020-04-22 21:02:46 +01:00
Lioncash
511613c736 frontend/A32/types: Use helper function in operator+ overload
Allows deduplicating an assert and a cast.
2020-04-22 21:02:46 +01:00
Lioncash
64e51a6d4d A32/disassembler_arm: Mark utility functions as static where applicable
These don't depend on class state and can be marked static to make that
explicit.
2020-04-22 21:02:46 +01:00
Lioncash
8316d231e9 A32: Implement barrier instructions introduced in ARMv7
Provides basic implementations of the barrier instruction introduced
within ARMv7. Currently these simply mirror the behavior of the AArch64
equivalents.
2020-04-22 21:02:46 +01:00
Lioncash
7fc3bd689d A32: Implement ARM-mode MLS 2020-04-22 21:02:46 +01:00
Lioncash
8b338b7def A32: Implement ARM-mode MOVT 2020-04-22 21:02:46 +01:00
Lioncash
877fa0f8c3 A32: Implement ARM-mode SBFX 2020-04-22 21:02:46 +01:00
Lioncash
47218ee65d A32: Implement ARM-mode UBFX 2020-04-22 21:02:46 +01:00
Lioncash
2970b34e3c A32: Implement ARM-mode BFI 2020-04-22 21:02:46 +01:00
Lioncash
fab3a59e05 A32: Implement ARM-mode BFC 2020-04-22 21:02:46 +01:00
Lioncash
7305d13221 A32: Implement ARM-mode RBIT 2020-04-22 21:02:46 +01:00
Lioncash
b2f7a0e7ba A32: Implement ARM-mode SDIV/UDIV
Now that we have Unicorn in place, we can freely implement instructions
introduced in newer versions of the ARM architecture.
2020-04-22 21:02:46 +01:00
Lioncash
c0ae23bbb7 A32/translate_thumb: Clean up formatting
Performs a similar tidying up of the Thumb translator, like what was
done with the regular ARM translator to make it consistent with the rest
of the codebase.

The A32 backend (both Thumb and ARM), will likely see more changes to it
in the near future, so this just acts as a "dusting off".
2020-04-22 21:02:46 +01:00
Merry
d7da53a74b Merge pull request #472 from lioncash/exception
general: Mark hash functions as noexcept
2020-04-22 21:01:44 +01:00
Lioncash
7bb5440507 general: Mark hash functions as noexcept
Generally hash functions shouldn't throw exceptions. It's also a
requirement for the standard library-provided hash functions to not
throw exceptions.

An exception to this rule is made for user-defined specializations,
however we can just be consistent with the standard library on this to
allow it to play nicer with it.

While we're at it, we can also make the std::less specializations
noexcpet as well, since they also can't throw.
2020-04-22 21:01:43 +01:00
Lioncash
fe95575b95 general: Replace unreachable-imitating assertions with UNREACHABLE()
We can just use the self-documenting assertion for indicating
unreachable paths, instead of manually passing false and providing a
message.
2020-04-22 21:01:43 +01:00
Lioncash
7c81a58ed3 frontend/ir/ir_emitter: Alter parameters of FPDoubleToSingle() and FPSingleToDouble() to pass along desired rounding mode
This will be necessary to special-case the non-IEEE Von Neumann rounding
to odd rounding mode.
2020-04-22 20:58:10 +01:00
Lioncash
05a6ab691d translate_arm/coprocessor: Minor tidying up 2020-04-22 20:58:10 +01:00
Lioncash
1e32a09c03 translate_arm/vfp2: Invert conditionals where applicable 2020-04-22 20:58:10 +01:00
Lioncash
e209b31073 translate_arm/synchronization: Invert conditionals where applicable 2020-04-22 20:58:10 +01:00