MerryMage
ed48a9d7d5
A32: Implement VFPv5 VRINTX
2020-06-24 22:31:58 +01:00
MerryMage
3ea49fc6d6
A32: Implement VFPv3 VCT (between floating-point and fixed-point)
2020-06-22 22:08:58 +01:00
MerryMage
52b8039367
A32: Implement VFPv5 VRINT{R,Z}
2020-06-22 19:35:32 +01:00
MerryMage
fda4e11887
A32: Implement ASIMD VMOV (general-purpose register to scalar)
2020-06-20 23:40:48 +01:00
MerryMage
7ec22b4e1d
A32: Implement ASIMD VMOV (scalar to general-purpose register)
2020-06-20 23:30:56 +01:00
MerryMage
e8c460c167
A32: Implement ASIMD VDUP (ARM core register)
2020-06-20 16:02:43 +01:00
MerryMage
ad96b2b18d
VFPv5: Implement VCVT{A,N,P,M}
2020-06-19 20:31:43 +01:00
MerryMage
6a965b80d6
VFPv5: Implement VRINT{A,N,P,M}
2020-06-19 20:24:13 +01:00
MerryMage
3e252cdbfc
VFPv5: Implement VSEL
2020-06-19 19:44:45 +01:00
MerryMage
669d05caca
VFPv5: Implement VMINNM
2020-06-19 19:44:45 +01:00
MerryMage
6e7ea151a3
VFPv5: Implement VMAXNM
2020-06-19 19:39:01 +01:00
MerryMage
e7f1a0d408
A32: ARMv8: Implement LDA{,EX}{,B,D,H} and STL{,EX}{,B,D,H}
2020-05-15 21:07:36 +01:00
MerryMage
59db2c191a
VFPv3: Implement VMOV (immediate)
2020-05-10 15:09:37 +01:00
MerryMage
3c86d58064
VFPv4: Implement VCVTB, VCVTT
2020-05-10 14:45:18 +01:00
MerryMage
010fab9a0e
VFPv4: Implement VFMA, VFMS
2020-05-10 14:20:11 +01:00
MerryMage
8e97b10acb
VFPv4: Implement VFNMS, VFNMA
2020-05-10 14:14:03 +01:00
MerryMage
9a38c7324f
A32: Add decoders for remaining v7 instructions
2020-05-10 10:50:34 +01:00
MerryMage
5c0bb5cc63
Remove unreachable code (MSVC warnings)
2020-04-23 16:36:34 +01:00
MerryMage
a8a712c801
Relicense to 0BSD
2020-04-23 15:45:57 +01:00
Lioncash
dddba94c17
disassembler_arm: Apply const where applicable
2020-04-22 21:04:22 +01:00
Lioncash
106c8c2473
A32: Implement ARM-mode MOVW
...
Introduced to the ISA in ARMv6T2
2020-04-22 21:02:47 +01:00
Lioncash
9a097e307f
A32: Implement the ARM-mode variant of SEVL
2020-04-22 21:02:47 +01:00
Lioncash
b902f72001
A32/disassembler_arm: Remove <unimplemented> from hint instruction output
...
Given we now support hooking these hint instructions, we can consider
them implemented.
2020-04-22 21:02:47 +01:00
Lioncash
0fa0bca22a
A32: Handle different variants of PLD
2020-04-22 21:02:47 +01:00
Merry
30d28029a8
Merge pull request #492 from lioncash/vfp
...
A32: Rename vfp2-related files to vfp
2020-04-22 21:02:47 +01:00
Lioncash
97277c598b
A32: Rename vfp2-related files to vfp
...
Now that we fuzz against Unicorn, we aren't just restricted to VFPv2.
VFPv3 and VFPv4 facilities can now be implemented. This renames
constructs mentioning VFPv2 to just refer to VFP.
2020-04-22 21:02:46 +01:00
Lioncash
e37689315d
A32: Implement ARM-mode CRC32 instructions
...
Implements the ARM-mode variants of the CRC32 instructions introduced
within ARMv8. This is also one of the instruction cases where there is
UNPREDICTABLE behavior that is constrained (we must do one of the
options indicated by the reference manual).
In both documented cases of constrained unpredictable behavior, we treat
the instructions as unpredictable in order to allow library users to
hook the unpredictable exception to provide the intended behavior they
desire.
2020-04-22 21:02:46 +01:00
Lioncash
4ba2318b2e
A32: Replace immediate type aliases with the Imm template
...
Replaces type aliases of raw integral types with the more type-safe Imm
template, like how the AArch64 frontend has been using it.
This makes the two frontends more consistent with one another.
2020-04-22 21:02:46 +01:00
Lioncash
64e51a6d4d
A32/disassembler_arm: Mark utility functions as static where applicable
...
These don't depend on class state and can be marked static to make that
explicit.
2020-04-22 21:02:46 +01:00
Lioncash
8316d231e9
A32: Implement barrier instructions introduced in ARMv7
...
Provides basic implementations of the barrier instruction introduced
within ARMv7. Currently these simply mirror the behavior of the AArch64
equivalents.
2020-04-22 21:02:46 +01:00
Lioncash
7fc3bd689d
A32: Implement ARM-mode MLS
2020-04-22 21:02:46 +01:00
Lioncash
8b338b7def
A32: Implement ARM-mode MOVT
2020-04-22 21:02:46 +01:00
Lioncash
877fa0f8c3
A32: Implement ARM-mode SBFX
2020-04-22 21:02:46 +01:00
Lioncash
47218ee65d
A32: Implement ARM-mode UBFX
2020-04-22 21:02:46 +01:00
Lioncash
2970b34e3c
A32: Implement ARM-mode BFI
2020-04-22 21:02:46 +01:00
Lioncash
fab3a59e05
A32: Implement ARM-mode BFC
2020-04-22 21:02:46 +01:00
Lioncash
7305d13221
A32: Implement ARM-mode RBIT
2020-04-22 21:02:46 +01:00
Lioncash
b2f7a0e7ba
A32: Implement ARM-mode SDIV/UDIV
...
Now that we have Unicorn in place, we can freely implement instructions
introduced in newer versions of the ARM architecture.
2020-04-22 21:02:46 +01:00
V.Kalyuzhny
764a93bf5a
Switch boost::optional to std::optional
2020-04-22 20:57:37 +01:00
MerryMage
f73104633b
a32_emit_x64: Fix incorrect BMI2 implementation for SetCpsr
...
* The MSB for each byte in cpsr_ge were not being appropriately set.
* We also expand test coverage to test this case.
* We fix the disassembly of the MSR (imm) and MSR (reg) instructions as well.
2020-04-22 20:53:46 +01:00
Lioncash
b38dd191bd
disassembler_arm: Remove rotation helper function in favor of Common::RotateRight
...
Mildly reduces the amount of duplicated behavior
2020-04-22 20:46:17 +01:00
Lioncash
67443efb62
General: Convert multiple namespace specifiers to nested namespace specifiers where applicable
...
Makes namespacing a little less noisy
2020-04-22 20:44:38 +01:00
MerryMage
b3c73e2622
Label A32 specific code appropriately
2020-04-22 20:33:30 +01:00
