mirror of
https://github.com/azahar-emu/dynarmic
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90 lines
2.8 KiB
C++
90 lines
2.8 KiB
C++
/* This file is part of the dynarmic project.
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* Copyright (c) 2016 MerryMage
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* SPDX-License-Identifier: 0BSD
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*/
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#include "frontend/A32/translate/impl/translate_arm.h"
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namespace Dynarmic::A32 {
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// RBIT<c> <Rd>, <Rm>
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bool ArmTranslatorVisitor::arm_RBIT(Cond cond, Reg d, Reg m) {
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if (d == Reg::PC || m == Reg::PC) {
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return UnpredictableInstruction();
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}
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if (!ConditionPassed(cond)) {
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return true;
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}
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const IR::U32 swapped = ir.ByteReverseWord(ir.GetRegister(m));
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// ((x & 0xF0F0F0F0) >> 4) | ((x & 0x0F0F0F0F) << 4)
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const IR::U32 first_lsr = ir.LogicalShiftRight(ir.And(swapped, ir.Imm32(0xF0F0F0F0)), ir.Imm8(4));
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const IR::U32 first_lsl = ir.LogicalShiftLeft(ir.And(swapped, ir.Imm32(0x0F0F0F0F)), ir.Imm8(4));
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const IR::U32 corrected = ir.Or(first_lsl, first_lsr);
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// ((x & 0x88888888) >> 3) | ((x & 0x44444444) >> 1) |
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// ((x & 0x22222222) << 1) | ((x & 0x11111111) << 3)
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const IR::U32 second_lsr = ir.LogicalShiftRight(ir.And(corrected, ir.Imm32(0x88888888)), ir.Imm8(3));
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const IR::U32 third_lsr = ir.LogicalShiftRight(ir.And(corrected, ir.Imm32(0x44444444)), ir.Imm8(1));
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const IR::U32 second_lsl = ir.LogicalShiftLeft(ir.And(corrected, ir.Imm32(0x22222222)), ir.Imm8(1));
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const IR::U32 third_lsl = ir.LogicalShiftLeft(ir.And(corrected, ir.Imm32(0x11111111)), ir.Imm8(3));
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const IR::U32 result = ir.Or(ir.Or(ir.Or(second_lsr, third_lsr), second_lsl), third_lsl);
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ir.SetRegister(d, result);
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return true;
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}
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// REV<c> <Rd>, <Rm>
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bool ArmTranslatorVisitor::arm_REV(Cond cond, Reg d, Reg m) {
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if (d == Reg::PC || m == Reg::PC) {
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return UnpredictableInstruction();
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}
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if (!ConditionPassed(cond)) {
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return true;
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}
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const auto result = ir.ByteReverseWord(ir.GetRegister(m));
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ir.SetRegister(d, result);
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return true;
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}
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// REV16<c> <Rd>, <Rm>
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bool ArmTranslatorVisitor::arm_REV16(Cond cond, Reg d, Reg m) {
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if (d == Reg::PC || m == Reg::PC) {
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return UnpredictableInstruction();
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}
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if (!ConditionPassed(cond)) {
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return true;
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}
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const auto reg_m = ir.GetRegister(m);
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const auto lo = ir.And(ir.LogicalShiftRight(reg_m, ir.Imm8(8), ir.Imm1(0)).result, ir.Imm32(0x00FF00FF));
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const auto hi = ir.And(ir.LogicalShiftLeft(reg_m, ir.Imm8(8), ir.Imm1(0)).result, ir.Imm32(0xFF00FF00));
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const auto result = ir.Or(lo, hi);
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ir.SetRegister(d, result);
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return true;
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}
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// REVSH<c> <Rd>, <Rm>
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bool ArmTranslatorVisitor::arm_REVSH(Cond cond, Reg d, Reg m) {
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if (d == Reg::PC || m == Reg::PC) {
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return UnpredictableInstruction();
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}
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if (!ConditionPassed(cond)) {
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return true;
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}
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const auto rev_half = ir.ByteReverseHalf(ir.LeastSignificantHalf(ir.GetRegister(m)));
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ir.SetRegister(d, ir.SignExtendHalfToWord(rev_half));
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return true;
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}
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} // namespace Dynarmic::A32
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