mirror of
https://github.com/azahar-emu/dynarmic
synced 2025-11-08 16:10:05 +01:00
0992987c98
The purpose of this instruction is to raise exceptions when certain decode-time issues happen, instead of asserting at translate time. This allows us to use the translator for code analysis without worrying about unnecessary asserts, but also provides flexibility for the library user to perform custom behaviour when one of these states are raised.
437 lines
11 KiB
C++
437 lines
11 KiB
C++
/* This file is part of the dynarmic project.
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* Copyright (c) 2016 MerryMage
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* This software may be used and distributed according to the terms of the GNU
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* General Public License version 2 or any later version.
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*/
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#include <algorithm>
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#include "common/assert.h"
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#include "frontend/ir/microinstruction.h"
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namespace Dynarmic {
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namespace IR {
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bool Inst::IsArithmeticShift() const {
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return op == Opcode::ArithmeticShiftRight32 ||
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op == Opcode::ArithmeticShiftRight64;
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}
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bool Inst::IsCircularShift() const {
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return op == Opcode::RotateRight32 ||
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op == Opcode::RotateRight64 ||
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op == Opcode::RotateRightExtended;
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}
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bool Inst::IsLogicalShift() const {
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switch (op) {
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case Opcode::LogicalShiftLeft32:
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case Opcode::LogicalShiftLeft64:
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case Opcode::LogicalShiftRight32:
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case Opcode::LogicalShiftRight64:
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return true;
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default:
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return false;
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}
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}
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bool Inst::IsShift() const {
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return IsArithmeticShift() ||
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IsCircularShift() ||
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IsLogicalShift();
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}
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bool Inst::IsSharedMemoryRead() const {
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switch (op) {
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case Opcode::A32ReadMemory8:
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case Opcode::A32ReadMemory16:
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case Opcode::A32ReadMemory32:
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case Opcode::A32ReadMemory64:
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case Opcode::A64ReadMemory8:
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case Opcode::A64ReadMemory16:
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case Opcode::A64ReadMemory32:
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case Opcode::A64ReadMemory64:
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return true;
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default:
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return false;
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}
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}
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bool Inst::IsSharedMemoryWrite() const {
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switch (op) {
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case Opcode::A32WriteMemory8:
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case Opcode::A32WriteMemory16:
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case Opcode::A32WriteMemory32:
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case Opcode::A32WriteMemory64:
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case Opcode::A64WriteMemory8:
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case Opcode::A64WriteMemory16:
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case Opcode::A64WriteMemory32:
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case Opcode::A64WriteMemory64:
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return true;
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default:
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return false;
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}
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}
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bool Inst::IsSharedMemoryReadOrWrite() const {
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return IsSharedMemoryRead() || IsSharedMemoryWrite();
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}
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bool Inst::IsExclusiveMemoryWrite() const {
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switch (op) {
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case Opcode::A32ExclusiveWriteMemory8:
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case Opcode::A32ExclusiveWriteMemory16:
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case Opcode::A32ExclusiveWriteMemory32:
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case Opcode::A32ExclusiveWriteMemory64:
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return true;
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default:
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return false;
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}
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}
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bool Inst::IsMemoryRead() const {
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return IsSharedMemoryRead();
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}
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bool Inst::IsMemoryWrite() const {
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return IsSharedMemoryWrite() || IsExclusiveMemoryWrite();
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}
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bool Inst::IsMemoryReadOrWrite() const {
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return IsMemoryRead() || IsMemoryWrite();
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}
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bool Inst::ReadsFromCPSR() const {
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switch (op) {
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case Opcode::A32GetCpsr:
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case Opcode::A32GetNFlag:
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case Opcode::A32GetZFlag:
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case Opcode::A32GetCFlag:
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case Opcode::A32GetVFlag:
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case Opcode::A32GetGEFlags:
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return true;
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default:
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return false;
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}
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}
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bool Inst::WritesToCPSR() const {
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switch (op) {
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case Opcode::A32SetCpsr:
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case Opcode::A32SetCpsrNZCV:
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case Opcode::A32SetCpsrNZCVQ:
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case Opcode::A32SetNFlag:
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case Opcode::A32SetZFlag:
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case Opcode::A32SetCFlag:
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case Opcode::A32SetVFlag:
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case Opcode::A32OrQFlag:
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case Opcode::A32SetGEFlags:
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case Opcode::A32SetGEFlagsCompressed:
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case Opcode::A64SetNZCV:
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return true;
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default:
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return false;
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}
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}
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bool Inst::ReadsFromCoreRegister() const {
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switch (op) {
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case Opcode::A32GetRegister:
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case Opcode::A32GetExtendedRegister32:
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case Opcode::A32GetExtendedRegister64:
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case Opcode::A64GetW:
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case Opcode::A64GetX:
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case Opcode::A64GetSP:
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return true;
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default:
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return false;
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}
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}
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bool Inst::WritesToCoreRegister() const {
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switch (op) {
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case Opcode::A32SetRegister:
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case Opcode::A32SetExtendedRegister32:
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case Opcode::A32SetExtendedRegister64:
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case Opcode::A32BXWritePC:
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case Opcode::A64SetW:
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case Opcode::A64SetX:
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case Opcode::A64SetSP:
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case Opcode::A64SetPC:
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return true;
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default:
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return false;
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}
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}
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bool Inst::ReadsFromFPSCR() const {
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switch (op) {
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case Opcode::A32GetFpscr:
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case Opcode::A32GetFpscrNZCV:
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case Opcode::FPAbs32:
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case Opcode::FPAbs64:
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case Opcode::FPAdd32:
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case Opcode::FPAdd64:
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case Opcode::FPCompare32:
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case Opcode::FPCompare64:
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case Opcode::FPDiv32:
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case Opcode::FPDiv64:
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case Opcode::FPMul32:
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case Opcode::FPMul64:
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case Opcode::FPNeg32:
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case Opcode::FPNeg64:
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case Opcode::FPSqrt32:
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case Opcode::FPSqrt64:
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case Opcode::FPSub32:
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case Opcode::FPSub64:
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return true;
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default:
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return false;
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}
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}
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bool Inst::WritesToFPSCR() const {
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switch (op) {
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case Opcode::A32SetFpscr:
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case Opcode::A32SetFpscrNZCV:
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case Opcode::FPAbs32:
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case Opcode::FPAbs64:
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case Opcode::FPAdd32:
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case Opcode::FPAdd64:
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case Opcode::FPCompare32:
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case Opcode::FPCompare64:
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case Opcode::FPDiv32:
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case Opcode::FPDiv64:
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case Opcode::FPMul32:
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case Opcode::FPMul64:
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case Opcode::FPNeg32:
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case Opcode::FPNeg64:
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case Opcode::FPSqrt32:
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case Opcode::FPSqrt64:
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case Opcode::FPSub32:
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case Opcode::FPSub64:
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return true;
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default:
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return false;
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}
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}
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bool Inst::CausesCPUException() const {
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return op == Opcode::Breakpoint ||
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op == Opcode::A32CallSupervisor ||
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op == Opcode::A64CallSupervisor ||
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op == Opcode::A64ExceptionRaised;
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}
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bool Inst::AltersExclusiveState() const {
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return op == Opcode::A32ClearExclusive ||
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op == Opcode::A32SetExclusive ||
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IsExclusiveMemoryWrite();
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}
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bool Inst::IsCoprocessorInstruction() const {
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switch (op) {
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case Opcode::A32CoprocInternalOperation:
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case Opcode::A32CoprocSendOneWord:
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case Opcode::A32CoprocSendTwoWords:
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case Opcode::A32CoprocGetOneWord:
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case Opcode::A32CoprocGetTwoWords:
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case Opcode::A32CoprocLoadWords:
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case Opcode::A32CoprocStoreWords:
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return true;
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default:
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return false;
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}
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}
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bool Inst::MayHaveSideEffects() const {
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return op == Opcode::PushRSB ||
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op == Opcode::A64SetCheckBit ||
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CausesCPUException() ||
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WritesToCoreRegister() ||
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WritesToCPSR() ||
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WritesToFPSCR() ||
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AltersExclusiveState() ||
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IsMemoryWrite() ||
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IsCoprocessorInstruction();
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}
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bool Inst::IsAPseudoOperation() const {
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switch (op) {
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case Opcode::GetCarryFromOp:
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case Opcode::GetOverflowFromOp:
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case Opcode::GetGEFromOp:
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case Opcode::GetNZCVFromOp:
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return true;
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default:
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return false;
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}
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}
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bool Inst::MayGetNZCVFromOp() const {
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switch (op) {
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case Opcode::Add32:
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case Opcode::Add64:
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case Opcode::Sub32:
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case Opcode::Sub64:
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case Opcode::And32:
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case Opcode::And64:
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case Opcode::Eor32:
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case Opcode::Eor64:
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case Opcode::Or32:
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case Opcode::Or64:
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case Opcode::Not32:
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case Opcode::Not64:
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return true;
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default:
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return false;
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}
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}
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bool Inst::AreAllArgsImmediates() const {
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return std::all_of(args.begin(), args.begin() + NumArgs(), [](const auto& value){ return value.IsImmediate(); });
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}
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bool Inst::HasAssociatedPseudoOperation() const {
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return carry_inst || overflow_inst || ge_inst || nzcv_inst;
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}
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Inst* Inst::GetAssociatedPseudoOperation(Opcode opcode) {
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// This is faster than doing a search through the block.
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switch (opcode) {
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case Opcode::GetCarryFromOp:
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ASSERT(!carry_inst || carry_inst->GetOpcode() == Opcode::GetCarryFromOp);
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return carry_inst;
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case Opcode::GetOverflowFromOp:
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ASSERT(!overflow_inst || overflow_inst->GetOpcode() == Opcode::GetOverflowFromOp);
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return overflow_inst;
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case Opcode::GetGEFromOp:
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ASSERT(!ge_inst || ge_inst->GetOpcode() == Opcode::GetGEFromOp);
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return ge_inst;
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case Opcode::GetNZCVFromOp:
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ASSERT(!nzcv_inst || nzcv_inst->GetOpcode() == Opcode::GetNZCVFromOp);
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return nzcv_inst;
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default:
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break;
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}
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ASSERT_MSG(false, "Not a valid pseudo-operation");
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return nullptr;
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}
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Type Inst::GetType() const {
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if (op == Opcode::Identity)
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return args[0].GetType();
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return GetTypeOf(op);
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}
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Value Inst::GetArg(size_t index) const {
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ASSERT(index < GetNumArgsOf(op));
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ASSERT(!args[index].IsEmpty());
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return args[index];
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}
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void Inst::SetArg(size_t index, Value value) {
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ASSERT(index < GetNumArgsOf(op));
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ASSERT(AreTypesCompatible(value.GetType(), GetArgTypeOf(op, index)));
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if (!args[index].IsImmediate()) {
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UndoUse(args[index]);
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}
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if (!value.IsImmediate()) {
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Use(value);
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}
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args[index] = value;
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}
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void Inst::Invalidate() {
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for (auto& value : args) {
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if (!value.IsImmediate()) {
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UndoUse(value);
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}
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value = {};
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}
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op = Opcode::Void;
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}
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void Inst::ReplaceUsesWith(Value replacement) {
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Invalidate();
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op = Opcode::Identity;
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if (!replacement.IsImmediate()) {
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Use(replacement);
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}
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args[0] = replacement;
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}
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void Inst::Use(const Value& value) {
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value.GetInst()->use_count++;
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switch (op){
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case Opcode::GetCarryFromOp:
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ASSERT_MSG(!value.GetInst()->carry_inst, "Only one of each type of pseudo-op allowed");
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value.GetInst()->carry_inst = this;
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break;
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case Opcode::GetOverflowFromOp:
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ASSERT_MSG(!value.GetInst()->overflow_inst, "Only one of each type of pseudo-op allowed");
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value.GetInst()->overflow_inst = this;
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break;
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case Opcode::GetGEFromOp:
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ASSERT_MSG(!value.GetInst()->ge_inst, "Only one of each type of pseudo-op allowed");
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value.GetInst()->ge_inst = this;
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break;
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case Opcode::GetNZCVFromOp:
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ASSERT_MSG(!value.GetInst()->nzcv_inst, "Only one of each type of pseudo-op allowed");
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ASSERT_MSG(value.GetInst()->MayGetNZCVFromOp(), "This value doesn't support the GetNZCVFromOp pseduo-op");
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value.GetInst()->nzcv_inst = this;
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break;
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default:
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break;
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}
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}
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void Inst::UndoUse(const Value& value) {
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value.GetInst()->use_count--;
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switch (op){
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case Opcode::GetCarryFromOp:
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ASSERT(value.GetInst()->carry_inst->GetOpcode() == Opcode::GetCarryFromOp);
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value.GetInst()->carry_inst = nullptr;
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break;
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case Opcode::GetOverflowFromOp:
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ASSERT(value.GetInst()->overflow_inst->GetOpcode() == Opcode::GetOverflowFromOp);
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value.GetInst()->overflow_inst = nullptr;
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break;
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case Opcode::GetGEFromOp:
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ASSERT(value.GetInst()->ge_inst->GetOpcode() == Opcode::GetGEFromOp);
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value.GetInst()->ge_inst = nullptr;
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break;
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case Opcode::GetNZCVFromOp:
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ASSERT(value.GetInst()->nzcv_inst->GetOpcode() == Opcode::GetNZCVFromOp);
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value.GetInst()->nzcv_inst = nullptr;
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break;
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default:
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break;
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}
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}
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} // namespace IR
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} // namespace Dynarmic
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