mirror of
https://github.com/azahar-emu/dynarmic
synced 2025-11-14 11:00:00 +01:00
af3614553b
These will be used by both frontends in the future, so this performs the migratory changes separate from the changes that will make use of them.
454 lines
13 KiB
C++
454 lines
13 KiB
C++
/* This file is part of the dynarmic project.
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* Copyright (c) 2018 MerryMage
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* This software may be used and distributed according to the terms of the GNU
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* General Public License version 2 or any later version.
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*/
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#include "common/bit_util.h"
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#include "frontend/ir/terminal.h"
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#include "frontend/A64/translate/impl/impl.h"
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namespace Dynarmic::A64 {
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bool TranslatorVisitor::InterpretThisInstruction() {
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ir.SetTerm(IR::Term::Interpret(*ir.current_location));
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return false;
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}
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bool TranslatorVisitor::UnpredictableInstruction() {
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return RaiseException(Exception::UnpredictableInstruction);
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}
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bool TranslatorVisitor::DecodeError() {
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UNREACHABLE();
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return false;
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}
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bool TranslatorVisitor::ReservedValue() {
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return RaiseException(Exception::ReservedValue);
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}
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bool TranslatorVisitor::UnallocatedEncoding() {
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return RaiseException(Exception::UnallocatedEncoding);
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}
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bool TranslatorVisitor::RaiseException(Exception exception) {
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ir.SetPC(ir.Imm64(ir.current_location->PC() + 4));
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ir.ExceptionRaised(exception);
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ir.SetTerm(IR::Term::CheckHalt{IR::Term::ReturnToDispatch{}});
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return false;
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}
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std::optional<TranslatorVisitor::BitMasks> TranslatorVisitor::DecodeBitMasks(bool immN, Imm<6> imms, Imm<6> immr, bool immediate) {
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const int len = Common::HighestSetBit((immN ? 1 << 6 : 0) | (imms.ZeroExtend() ^ 0b111111));
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if (len < 1) {
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return std::nullopt;
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}
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const size_t levels = Common::Ones<size_t>(len);
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if (immediate && (imms.ZeroExtend() & levels) == levels) {
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return std::nullopt;
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}
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const s32 S = s32(imms.ZeroExtend() & levels);
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const s32 R = s32(immr.ZeroExtend() & levels);
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const u64 d = u64(S - R) & levels;
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const size_t esize = size_t{1} << len;
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const u64 welem = Common::Ones<u64>(S + 1);
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const u64 telem = Common::Ones<u64>(d + 1);
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const u64 wmask = Common::RotateRight(Common::Replicate(welem, esize), R);
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const u64 tmask = Common::Replicate(telem, esize);
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return BitMasks{wmask, tmask};
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}
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u64 TranslatorVisitor::AdvSIMDExpandImm(bool op, Imm<4> cmode, Imm<8> imm8) {
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switch (cmode.Bits<1, 3>()) {
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case 0b000:
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return Common::Replicate<u64>(imm8.ZeroExtend<u64>(), 32);
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case 0b001:
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return Common::Replicate<u64>(imm8.ZeroExtend<u64>() << 8, 32);
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case 0b010:
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return Common::Replicate<u64>(imm8.ZeroExtend<u64>() << 16, 32);
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case 0b011:
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return Common::Replicate<u64>(imm8.ZeroExtend<u64>() << 24, 32);
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case 0b100:
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return Common::Replicate<u64>(imm8.ZeroExtend<u64>(), 16);
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case 0b101:
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return Common::Replicate<u64>(imm8.ZeroExtend<u64>() << 8, 16);
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case 0b110:
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if (!cmode.Bit<0>()) {
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return Common::Replicate<u64>((imm8.ZeroExtend<u64>() << 8) | Common::Ones<u64>(8), 32);
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}
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return Common::Replicate<u64>((imm8.ZeroExtend<u64>() << 16) | Common::Ones<u64>(16), 32);
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case 0b111:
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if (!cmode.Bit<0>() && !op) {
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return Common::Replicate<u64>(imm8.ZeroExtend<u64>(), 8);
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}
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if (!cmode.Bit<0>() && op) {
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u64 result = 0;
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result |= imm8.Bit<0>() ? Common::Ones<u64>(8) << (0 * 8) : 0;
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result |= imm8.Bit<1>() ? Common::Ones<u64>(8) << (1 * 8) : 0;
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result |= imm8.Bit<2>() ? Common::Ones<u64>(8) << (2 * 8) : 0;
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result |= imm8.Bit<3>() ? Common::Ones<u64>(8) << (3 * 8) : 0;
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result |= imm8.Bit<4>() ? Common::Ones<u64>(8) << (4 * 8) : 0;
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result |= imm8.Bit<5>() ? Common::Ones<u64>(8) << (5 * 8) : 0;
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result |= imm8.Bit<6>() ? Common::Ones<u64>(8) << (6 * 8) : 0;
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result |= imm8.Bit<7>() ? Common::Ones<u64>(8) << (7 * 8) : 0;
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return result;
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}
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if (cmode.Bit<0>() && !op) {
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u64 result = 0;
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result |= imm8.Bit<7>() ? 0x80000000 : 0;
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result |= imm8.Bit<6>() ? 0x3E000000 : 0x40000000;
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result |= imm8.Bits<0, 5, u64>() << 19;
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return Common::Replicate<u64>(result, 32);
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}
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if (cmode.Bit<0>() && op) {
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u64 result = 0;
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result |= imm8.Bit<7>() ? 0x80000000'00000000 : 0;
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result |= imm8.Bit<6>() ? 0x3FC00000'00000000 : 0x40000000'00000000;
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result |= imm8.Bits<0, 5, u64>() << 48;
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return result;
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}
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}
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UNREACHABLE();
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return 0;
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}
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IR::UAny TranslatorVisitor::I(size_t bitsize, u64 value) {
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switch (bitsize) {
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case 8:
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return ir.Imm8(static_cast<u8>(value));
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case 16:
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return ir.Imm16(static_cast<u16>(value));
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case 32:
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return ir.Imm32(static_cast<u32>(value));
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case 64:
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return ir.Imm64(value);
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default:
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ASSERT_MSG(false, "Imm - get: Invalid bitsize");
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return {};
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}
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}
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IR::UAny TranslatorVisitor::X(size_t bitsize, Reg reg) {
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switch (bitsize) {
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case 8:
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return ir.LeastSignificantByte(ir.GetW(reg));
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case 16:
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return ir.LeastSignificantHalf(ir.GetW(reg));
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case 32:
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return ir.GetW(reg);
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case 64:
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return ir.GetX(reg);
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default:
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ASSERT_MSG(false, "X - get: Invalid bitsize");
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return {};
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}
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}
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void TranslatorVisitor::X(size_t bitsize, Reg reg, IR::U32U64 value) {
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switch (bitsize) {
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case 32:
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ir.SetW(reg, value);
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return;
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case 64:
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ir.SetX(reg, value);
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return;
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default:
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ASSERT_MSG(false, "X - set: Invalid bitsize");
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}
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}
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IR::U32U64 TranslatorVisitor::SP(size_t bitsize) {
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switch (bitsize) {
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case 32:
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return ir.LeastSignificantWord(ir.GetSP());
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case 64:
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return ir.GetSP();
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default:
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ASSERT_MSG(false, "SP - get : Invalid bitsize");
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return {};
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}
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}
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void TranslatorVisitor::SP(size_t bitsize, IR::U32U64 value) {
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switch (bitsize) {
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case 32:
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ir.SetSP(ir.ZeroExtendWordToLong(value));
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break;
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case 64:
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ir.SetSP(value);
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break;
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default:
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ASSERT_MSG(false, "SP - set : Invalid bitsize");
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}
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}
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IR::U128 TranslatorVisitor::V(size_t bitsize, Vec vec) {
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switch (bitsize) {
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case 32:
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return ir.GetS(vec);
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case 64:
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return ir.GetD(vec);
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case 128:
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return ir.GetQ(vec);
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default:
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ASSERT_MSG(false, "V - get : Invalid bitsize");
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}
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}
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void TranslatorVisitor::V(size_t bitsize, Vec vec, IR::U128 value) {
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switch (bitsize) {
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case 32:
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ir.SetS(vec, value);
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return;
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case 64:
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// TODO: Remove VectorZeroUpper when possible.
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ir.SetD(vec, ir.VectorZeroUpper(value));
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return;
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case 128:
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ir.SetQ(vec, value);
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return;
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default:
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ASSERT_MSG(false, "V - Set : Invalid bitsize");
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}
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}
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IR::UAnyU128 TranslatorVisitor::V_scalar(size_t bitsize, Vec vec) {
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if (bitsize == 128) {
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return V(128, vec);
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}
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// TODO: Optimize
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return ir.VectorGetElement(bitsize, ir.GetQ(vec), 0);
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}
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void TranslatorVisitor::V_scalar(size_t bitsize, Vec vec, IR::UAnyU128 value) {
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if (bitsize == 128) {
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V(128, vec, value);
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return;
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}
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// TODO: Optimize
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ir.SetQ(vec, ir.ZeroExtendToQuad(value));
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}
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IR::U128 TranslatorVisitor::Vpart(size_t bitsize, Vec vec, size_t part) {
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ASSERT(part == 0 || part == 1);
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ASSERT(bitsize == 64);
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if (part == 0) {
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return V(64, vec);
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}
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return ir.ZeroExtendToQuad(ir.VectorGetElement(bitsize, V(128, vec), part));
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}
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void TranslatorVisitor::Vpart(size_t bitsize, Vec vec, size_t part, IR::U128 value) {
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ASSERT(part == 0 || part == 1);
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if (part == 0) {
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ASSERT(bitsize == 64);
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V(128, vec, ir.VectorZeroExtend(bitsize, value));
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} else {
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ASSERT(bitsize == 64);
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V(128, vec, ir.VectorInterleaveLower(64, V(128, vec), value));
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}
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}
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IR::UAny TranslatorVisitor::Vpart_scalar(size_t bitsize, Vec vec, size_t part) {
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ASSERT(part == 0 || part == 1);
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if (part == 0) {
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ASSERT(bitsize == 8 || bitsize == 16 || bitsize == 32 || bitsize == 64);
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} else {
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ASSERT(bitsize == 64);
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}
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return ir.VectorGetElement(bitsize, V(128, vec), part);
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}
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void TranslatorVisitor::Vpart_scalar(size_t bitsize, Vec vec, size_t part, IR::UAny value) {
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ASSERT(part == 0 || part == 1);
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if (part == 0) {
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ASSERT(bitsize == 8 || bitsize == 16 || bitsize == 32 || bitsize == 64);
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V(128, vec, ir.ZeroExtendToQuad(value));
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} else {
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ASSERT(bitsize == 64);
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V(128, vec, ir.VectorSetElement(64, V(128, vec), 1, value));
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}
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}
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IR::UAnyU128 TranslatorVisitor::Mem(IR::U64 address, size_t bytesize, IR::AccType /*acc_type*/) {
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switch (bytesize) {
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case 1:
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return ir.ReadMemory8(address);
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case 2:
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return ir.ReadMemory16(address);
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case 4:
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return ir.ReadMemory32(address);
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case 8:
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return ir.ReadMemory64(address);
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case 16:
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return ir.ReadMemory128(address);
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default:
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ASSERT_MSG(false, "Invalid bytesize parameter {}", bytesize);
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return {};
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}
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}
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void TranslatorVisitor::Mem(IR::U64 address, size_t bytesize, IR::AccType /*acc_type*/, IR::UAnyU128 value) {
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switch (bytesize) {
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case 1:
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ir.WriteMemory8(address, value);
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return;
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case 2:
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ir.WriteMemory16(address, value);
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return;
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case 4:
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ir.WriteMemory32(address, value);
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return;
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case 8:
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ir.WriteMemory64(address, value);
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return;
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case 16:
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ir.WriteMemory128(address, value);
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return;
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default:
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ASSERT_MSG(false, "Invalid bytesize parameter {}", bytesize);
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return;
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}
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}
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IR::U32 TranslatorVisitor::ExclusiveMem(IR::U64 address, size_t bytesize, IR::AccType /*acc_type*/, IR::UAnyU128 value) {
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switch (bytesize) {
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case 1:
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return ir.ExclusiveWriteMemory8(address, value);
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case 2:
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return ir.ExclusiveWriteMemory16(address, value);
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case 4:
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return ir.ExclusiveWriteMemory32(address, value);
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case 8:
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return ir.ExclusiveWriteMemory64(address, value);
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case 16:
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return ir.ExclusiveWriteMemory128(address, value);
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default:
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ASSERT_MSG(false, "Invalid bytesize parameter {}", bytesize);
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return {};
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}
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}
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IR::U32U64 TranslatorVisitor::SignExtend(IR::UAny value, size_t to_size) {
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switch (to_size) {
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case 32:
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return ir.SignExtendToWord(value);
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case 64:
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return ir.SignExtendToLong(value);
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default:
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ASSERT_MSG(false, "Invalid size parameter {}", to_size);
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return {};
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}
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}
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IR::U32U64 TranslatorVisitor::ZeroExtend(IR::UAny value, size_t to_size) {
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switch (to_size) {
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case 32:
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return ir.ZeroExtendToWord(value);
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case 64:
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return ir.ZeroExtendToLong(value);
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default:
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ASSERT_MSG(false, "Invalid size parameter {}", to_size);
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return {};
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}
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}
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IR::U32U64 TranslatorVisitor::ShiftReg(size_t bitsize, Reg reg, Imm<2> shift, IR::U8 amount) {
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IR::U32U64 result = X(bitsize, reg);
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switch (shift.ZeroExtend()) {
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case 0b00:
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return ir.LogicalShiftLeft(result, amount);
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case 0b01:
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return ir.LogicalShiftRight(result, amount);
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case 0b10:
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return ir.ArithmeticShiftRight(result, amount);
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case 0b11:
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return ir.RotateRight(result, amount);
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}
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UNREACHABLE();
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return {};
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}
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IR::U32U64 TranslatorVisitor::ExtendReg(size_t bitsize, Reg reg, Imm<3> option, u8 shift) {
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ASSERT(shift <= 4);
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ASSERT(bitsize == 32 || bitsize == 64);
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IR::UAny val = X(bitsize, reg);
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size_t len;
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IR::U32U64 extended;
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bool signed_extend;
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switch (option.ZeroExtend()) {
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case 0b000: { // UXTB
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val = ir.LeastSignificantByte(val);
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len = 8;
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signed_extend = false;
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break;
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}
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case 0b001: { // UXTH
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val = ir.LeastSignificantHalf(val);
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len = 16;
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signed_extend = false;
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break;
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}
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case 0b010: { // UXTW
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if (bitsize != 32) {
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val = ir.LeastSignificantWord(val);
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}
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len = 32;
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signed_extend = false;
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break;
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}
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case 0b011: { // UXTX
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len = 64;
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signed_extend = false;
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break;
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}
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case 0b100: { // SXTB
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val = ir.LeastSignificantByte(val);
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len = 8;
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signed_extend = true;
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break;
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}
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case 0b101: { // SXTH
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val = ir.LeastSignificantHalf(val);
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len = 16;
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signed_extend = true;
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break;
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}
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case 0b110: { // SXTW
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if (bitsize != 32) {
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val = ir.LeastSignificantWord(val);
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}
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len = 32;
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signed_extend = true;
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break;
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}
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case 0b111: { // SXTX
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len = 64;
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signed_extend = true;
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break;
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}
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default:
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UNREACHABLE();
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}
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if (len < bitsize) {
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if (bitsize == 32) {
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extended = signed_extend ? ir.SignExtendToWord(val) : ir.ZeroExtendToWord(val);
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} else {
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extended = signed_extend ? ir.SignExtendToLong(val) : ir.ZeroExtendToLong(val);
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}
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} else {
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extended = val;
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}
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return ir.LogicalShiftLeft(extended, ir.Imm8(shift));
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}
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} // namespace Dynarmic::A64
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