mirror of
https://github.com/azahar-emu/dynarmic
synced 2025-11-07 15:40:00 +01:00
792 lines
24 KiB
C++
792 lines
24 KiB
C++
/* This file is part of the dynarmic project.
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* Copyright (c) 2018 MerryMage
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* This software may be used and distributed according to the terms of the GNU
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* General Public License version 2 or any later version.
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*/
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#include "frontend/A64/translate/impl/impl.h"
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namespace Dynarmic::A64 {
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namespace {
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enum class HighNarrowingOp {
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Add,
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Subtract,
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};
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enum class ExtraBehavior {
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None,
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Round
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};
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static void HighNarrowingOperation(TranslatorVisitor& v, bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd,
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HighNarrowingOp op, ExtraBehavior behavior) {
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const size_t part = Q;
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const size_t esize = 8 << size.ZeroExtend();
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const size_t doubled_esize = 2 * esize;
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const IR::U128 operand1 = v.ir.GetQ(Vn);
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const IR::U128 operand2 = v.ir.GetQ(Vm);
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IR::U128 wide = [&] {
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if (op == HighNarrowingOp::Add) {
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return v.ir.VectorAdd(doubled_esize, operand1, operand2);
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}
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return v.ir.VectorSub(doubled_esize, operand1, operand2);
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}();
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if (behavior == ExtraBehavior::Round) {
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const u64 round_const = 1ULL << (esize - 1);
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const IR::U128 round_operand = v.ir.VectorBroadcast(doubled_esize, v.I(doubled_esize, round_const));
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wide = v.ir.VectorAdd(doubled_esize, wide, round_operand);
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}
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const IR::U128 result = v.ir.VectorNarrow(doubled_esize,
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v.ir.VectorLogicalShiftRight(doubled_esize, wide, static_cast<u8>(esize)));
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v.Vpart(64, Vd, part, result);
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}
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enum class AbsDiffExtraBehavior {
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None,
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Accumulate
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};
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bool SignedAbsoluteDifference(TranslatorVisitor& v, bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd, AbsDiffExtraBehavior behavior) {
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if (size == 0b11) {
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return v.ReservedValue();
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}
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const size_t datasize = Q ? 128 : 64;
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const size_t esize = 8 << size.ZeroExtend();
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const IR::U128 operand1 = v.V(datasize, Vn);
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const IR::U128 operand2 = v.V(datasize, Vm);
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const IR::U128 result = [&] {
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const IR::U128 tmp = v.ir.VectorSignedAbsoluteDifference(esize, operand1, operand2);
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if (behavior == AbsDiffExtraBehavior::Accumulate) {
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const IR::U128 d = v.V(datasize, Vd);
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return v.ir.VectorAdd(esize, d, tmp);
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}
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return tmp;
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}();
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v.V(datasize, Vd, result);
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return true;
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}
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enum class Signedness {
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Signed,
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Unsigned
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};
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bool RoundingHalvingAdd(TranslatorVisitor& v, bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd, Signedness sign) {
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if (size == 0b11) {
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return v.ReservedValue();
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}
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const size_t esize = 8 << size.ZeroExtend();
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const size_t datasize = Q ? 128 : 64;
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const IR::U128 operand1 = v.V(datasize, Vm);
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const IR::U128 operand2 = v.V(datasize, Vn);
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const IR::U128 result = sign == Signedness::Signed ? v.ir.VectorRoundingHalvingAddSigned(esize, operand1, operand2)
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: v.ir.VectorRoundingHalvingAddUnsigned(esize, operand1, operand2);
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v.V(datasize, Vd, result);
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return true;
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}
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enum class ComparisonType {
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EQ,
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GE,
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AbsoluteGE,
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GT,
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AbsoluteGT
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};
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bool FPCompareRegister(TranslatorVisitor& v, bool Q, bool sz, Vec Vm, Vec Vn, Vec Vd, ComparisonType type) {
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if (sz && !Q) {
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return v.ReservedValue();
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}
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const size_t esize = sz ? 64 : 32;
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const size_t datasize = Q ? 128 : 64;
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const IR::U128 operand1 = v.V(datasize, Vn);
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const IR::U128 operand2 = v.V(datasize, Vm);
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const IR::U128 result = [&] {
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switch (type) {
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case ComparisonType::EQ:
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return v.ir.FPVectorEqual(esize, operand1, operand2);
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case ComparisonType::GE:
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return v.ir.FPVectorGreaterEqual(esize, operand1, operand2);
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case ComparisonType::AbsoluteGE:
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return v.ir.FPVectorGreaterEqual(esize,
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v.ir.FPVectorAbs(esize, operand1),
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v.ir.FPVectorAbs(esize, operand2));
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case ComparisonType::GT:
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return v.ir.FPVectorGreater(esize, operand1, operand2);
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case ComparisonType::AbsoluteGT:
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return v.ir.FPVectorGreater(esize,
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v.ir.FPVectorAbs(esize, operand1),
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v.ir.FPVectorAbs(esize, operand2));
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}
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UNREACHABLE();
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return IR::U128{};
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}();
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v.V(datasize, Vd, result);
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return true;
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}
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} // Anonymous namespace
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bool TranslatorVisitor::CMGT_reg_2(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
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if (size == 0b11 && !Q) return ReservedValue();
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const size_t esize = 8 << size.ZeroExtend<size_t>();
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const size_t datasize = Q ? 128 : 64;
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const IR::U128 operand1 = V(datasize, Vn);
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const IR::U128 operand2 = V(datasize, Vm);
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const IR::U128 result = ir.VectorGreaterSigned(esize, operand1, operand2);
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V(datasize, Vd, result);
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return true;
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}
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bool TranslatorVisitor::CMGE_reg_2(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
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if (size == 0b11 && !Q) return ReservedValue();
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const size_t esize = 8 << size.ZeroExtend<size_t>();
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const size_t datasize = Q ? 128 : 64;
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const IR::U128 operand1 = V(datasize, Vn);
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const IR::U128 operand2 = V(datasize, Vm);
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IR::U128 result = ir.VectorGreaterEqualSigned(esize, operand1, operand2);
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if (datasize == 64) {
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result = ir.VectorZeroUpper(result);
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}
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V(datasize, Vd, result);
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return true;
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}
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bool TranslatorVisitor::SABA(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
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return SignedAbsoluteDifference(*this, Q, size, Vm, Vn, Vd, AbsDiffExtraBehavior::Accumulate);
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}
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bool TranslatorVisitor::SABD(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
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return SignedAbsoluteDifference(*this, Q, size, Vm, Vn, Vd, AbsDiffExtraBehavior::None);
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}
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bool TranslatorVisitor::SMAX(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
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if (size == 0b11) {
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return ReservedValue();
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}
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const size_t esize = 8 << size.ZeroExtend<size_t>();
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const size_t datasize = Q ? 128 : 64;
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const IR::U128 operand1 = V(datasize, Vn);
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const IR::U128 operand2 = V(datasize, Vm);
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const IR::U128 result = ir.VectorMaxSigned(esize, operand1, operand2);
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V(datasize, Vd, result);
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return true;
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}
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bool TranslatorVisitor::SMIN(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
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if (size == 0b11) {
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return ReservedValue();
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}
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const size_t esize = 8 << size.ZeroExtend<size_t>();
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const size_t datasize = Q ? 128 : 64;
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const IR::U128 operand1 = V(datasize, Vn);
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const IR::U128 operand2 = V(datasize, Vm);
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const IR::U128 result = ir.VectorMinSigned(esize, operand1, operand2);
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V(datasize, Vd, result);
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return true;
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}
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bool TranslatorVisitor::ADD_vector(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
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if (size == 0b11 && !Q) return ReservedValue();
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const size_t esize = 8 << size.ZeroExtend<size_t>();
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const size_t datasize = Q ? 128 : 64;
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auto operand1 = V(datasize, Vn);
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auto operand2 = V(datasize, Vm);
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auto result = ir.VectorAdd(esize, operand1, operand2);
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V(datasize, Vd, result);
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return true;
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}
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bool TranslatorVisitor::MLA_vec(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
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if (size == 0b11) return ReservedValue();
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const size_t esize = 8 << size.ZeroExtend<size_t>();
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const size_t datasize = Q ? 128 : 64;
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const IR::U128 operand1 = V(datasize, Vn);
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const IR::U128 operand2 = V(datasize, Vm);
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const IR::U128 operand3 = V(datasize, Vd);
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const IR::U128 result = ir.VectorAdd(esize, ir.VectorMultiply(esize, operand1, operand2), operand3);
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V(datasize, Vd, result);
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return true;
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}
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bool TranslatorVisitor::MUL_vec(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
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if (size == 0b11) return ReservedValue();
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const size_t esize = 8 << size.ZeroExtend<size_t>();
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const size_t datasize = Q ? 128 : 64;
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const IR::U128 operand1 = V(datasize, Vn);
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const IR::U128 operand2 = V(datasize, Vm);
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const IR::U128 result = ir.VectorMultiply(esize, operand1, operand2);
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V(datasize, Vd, result);
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return true;
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}
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bool TranslatorVisitor::ADDHN(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
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if (size == 0b11) {
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return ReservedValue();
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}
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HighNarrowingOperation(*this, Q, size, Vm, Vn, Vd, HighNarrowingOp::Add, ExtraBehavior::None);
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return true;
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}
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bool TranslatorVisitor::RADDHN(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
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if (size == 0b11) {
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return ReservedValue();
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}
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HighNarrowingOperation(*this, Q, size, Vm, Vn, Vd, HighNarrowingOp::Add, ExtraBehavior::Round);
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return true;
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}
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bool TranslatorVisitor::SUBHN(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
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if (size == 0b11) {
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return ReservedValue();
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}
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HighNarrowingOperation(*this, Q, size, Vm, Vn, Vd, HighNarrowingOp::Subtract, ExtraBehavior::None);
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return true;
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}
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bool TranslatorVisitor::RSUBHN(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
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if (size == 0b11) {
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return ReservedValue();
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}
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HighNarrowingOperation(*this, Q, size, Vm, Vn, Vd, HighNarrowingOp::Subtract, ExtraBehavior::Round);
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return true;
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}
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bool TranslatorVisitor::SHADD(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
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if (size == 0b11) {
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return ReservedValue();
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}
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const size_t datasize = Q ? 128 : 64;
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const size_t esize = 8 << size.ZeroExtend();
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const IR::U128 operand1 = V(datasize, Vn);
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const IR::U128 operand2 = V(datasize, Vm);
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const IR::U128 result = ir.VectorHalvingAddSigned(esize, operand1, operand2);
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V(datasize, Vd, result);
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return true;
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}
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bool TranslatorVisitor::SHSUB(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
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if (size == 0b11) {
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return ReservedValue();
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}
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const size_t datasize = Q ? 128 : 64;
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const size_t esize = 8 << size.ZeroExtend();
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const IR::U128 operand1 = V(datasize, Vn);
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const IR::U128 operand2 = V(datasize, Vm);
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const IR::U128 result = ir.VectorHalvingSubSigned(esize, operand1, operand2);
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V(datasize, Vd, result);
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return true;
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}
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bool TranslatorVisitor::SRHADD(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
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return RoundingHalvingAdd(*this, Q, size, Vm, Vn, Vd, Signedness::Signed);
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}
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bool TranslatorVisitor::UHADD(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
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if (size == 0b11) {
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return ReservedValue();
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}
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const size_t datasize = Q ? 128 : 64;
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const size_t esize = 8 << size.ZeroExtend();
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const IR::U128 operand1 = V(datasize, Vn);
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const IR::U128 operand2 = V(datasize, Vm);
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const IR::U128 result = ir.VectorHalvingAddUnsigned(esize, operand1, operand2);
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V(datasize, Vd, result);
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return true;
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}
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bool TranslatorVisitor::UHSUB(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
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if (size == 0b11) {
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return ReservedValue();
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}
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const size_t datasize = Q ? 128 : 64;
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const size_t esize = 8 << size.ZeroExtend();
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const IR::U128 operand1 = V(datasize, Vn);
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const IR::U128 operand2 = V(datasize, Vm);
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const IR::U128 result = ir.VectorHalvingSubUnsigned(esize, operand1, operand2);
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V(datasize, Vd, result);
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return true;
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}
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bool TranslatorVisitor::URHADD(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
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return RoundingHalvingAdd(*this, Q, size, Vm, Vn, Vd, Signedness::Unsigned);
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}
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bool TranslatorVisitor::ADDP_vec(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
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if (size == 0b11 && !Q) return ReservedValue();
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const size_t esize = 8 << size.ZeroExtend<size_t>();
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const size_t datasize = Q ? 128 : 64;
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const IR::U128 operand1 = V(datasize, Vn);
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const IR::U128 operand2 = V(datasize, Vm);
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const IR::U128 result = Q ? ir.VectorPairedAdd(esize, operand1, operand2) : ir.VectorPairedAddLower(esize, operand1, operand2);
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V(datasize, Vd, result);
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return true;
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}
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bool TranslatorVisitor::FABD_4(bool Q, bool sz, Vec Vm, Vec Vn, Vec Vd) {
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if (sz && !Q) {
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return ReservedValue();
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}
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const size_t datasize = Q ? 128 : 64;
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const size_t esize = sz ? 64 : 32;
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const IR::U128 operand1 = V(datasize, Vn);
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const IR::U128 operand2 = V(datasize, Vm);
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const IR::U128 result = ir.FPVectorAbs(esize, ir.FPVectorSub(esize, operand1, operand2));
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V(datasize, Vd, result);
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return true;
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}
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bool TranslatorVisitor::FACGE_4(bool Q, bool sz, Vec Vm, Vec Vn, Vec Vd) {
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return FPCompareRegister(*this, Q, sz, Vm, Vn, Vd, ComparisonType::AbsoluteGE);
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}
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bool TranslatorVisitor::FACGT_4(bool Q, bool sz, Vec Vm, Vec Vn, Vec Vd) {
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return FPCompareRegister(*this, Q, sz, Vm, Vn, Vd, ComparisonType::AbsoluteGT);
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}
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bool TranslatorVisitor::FADD_2(bool Q, bool sz, Vec Vm, Vec Vn, Vec Vd) {
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if (sz && !Q) {
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return ReservedValue();
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}
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const size_t esize = sz ? 64 : 32;
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const size_t datasize = Q ? 128 : 64;
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const IR::U128 operand1 = V(datasize, Vn);
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const IR::U128 operand2 = V(datasize, Vm);
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const IR::U128 result = ir.FPVectorAdd(esize, operand1, operand2);
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V(datasize, Vd, result);
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return true;
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}
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bool TranslatorVisitor::FCMEQ_reg_4(bool Q, bool sz, Vec Vm, Vec Vn, Vec Vd) {
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return FPCompareRegister(*this, Q, sz, Vm, Vn, Vd, ComparisonType::EQ);
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}
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bool TranslatorVisitor::FCMGE_reg_4(bool Q, bool sz, Vec Vm, Vec Vn, Vec Vd) {
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return FPCompareRegister(*this, Q, sz, Vm, Vn, Vd, ComparisonType::GE);
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}
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bool TranslatorVisitor::FCMGT_reg_4(bool Q, bool sz, Vec Vm, Vec Vn, Vec Vd) {
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return FPCompareRegister(*this, Q, sz, Vm, Vn, Vd, ComparisonType::GT);
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}
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bool TranslatorVisitor::AND_asimd(bool Q, Vec Vm, Vec Vn, Vec Vd) {
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const size_t datasize = Q ? 128 : 64;
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auto operand1 = V(datasize, Vn);
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auto operand2 = V(datasize, Vm);
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auto result = ir.VectorAnd(operand1, operand2);
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V(datasize, Vd, result);
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return true;
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}
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bool TranslatorVisitor::BIC_asimd_reg(bool Q, Vec Vm, Vec Vn, Vec Vd) {
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const size_t datasize = Q ? 128 : 64;
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const IR::U128 operand1 = V(datasize, Vn);
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const IR::U128 operand2 = V(datasize, Vm);
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IR::U128 result = ir.VectorAnd(operand1, ir.VectorNot(operand2));
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if (datasize == 64) {
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result = ir.VectorZeroUpper(result);
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}
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V(datasize, Vd, result);
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return true;
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}
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bool TranslatorVisitor::CMHI_2(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
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if (size == 0b11 && !Q) {
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return ReservedValue();
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}
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const size_t esize = 8 << size.ZeroExtend<size_t>();
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const size_t datasize = Q ? 128 : 64;
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const IR::U128 operand1 = V(datasize, Vn);
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const IR::U128 operand2 = V(datasize, Vm);
|
|
const IR::U128 result = ir.VectorGreaterUnsigned(esize, operand1, operand2);
|
|
V(datasize, Vd, result);
|
|
return true;
|
|
}
|
|
|
|
bool TranslatorVisitor::CMHS_2(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
|
|
if (size == 0b11 && !Q) {
|
|
return ReservedValue();
|
|
}
|
|
const size_t esize = 8 << size.ZeroExtend<size_t>();
|
|
const size_t datasize = Q ? 128 : 64;
|
|
|
|
const IR::U128 operand1 = V(datasize, Vn);
|
|
const IR::U128 operand2 = V(datasize, Vm);
|
|
IR::U128 result = ir.VectorGreaterEqualUnsigned(esize, operand1, operand2);
|
|
if (datasize == 64) {
|
|
result = ir.VectorZeroUpper(result);
|
|
}
|
|
V(datasize, Vd, result);
|
|
return true;
|
|
}
|
|
|
|
bool TranslatorVisitor::CMTST_2(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
|
|
if (size == 0b11 && !Q) {
|
|
return ReservedValue();
|
|
}
|
|
|
|
const size_t datasize = Q ? 128 : 64;
|
|
const size_t esize = 8 << size.ZeroExtend();
|
|
|
|
const IR::U128 operand1 = V(datasize, Vn);
|
|
const IR::U128 operand2 = V(datasize, Vm);
|
|
const IR::U128 anded = ir.VectorAnd(operand1, operand2);
|
|
const IR::U128 result = ir.VectorNot(ir.VectorEqual(esize, anded, ir.ZeroVector()));
|
|
|
|
V(datasize, Vd, result);
|
|
return true;
|
|
}
|
|
|
|
bool TranslatorVisitor::SSHL_2(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
|
|
if (size == 0b11 && !Q) {
|
|
return ReservedValue();
|
|
}
|
|
const size_t esize = 8 << size.ZeroExtend();
|
|
const size_t datasize = Q ? 128 : 64;
|
|
|
|
const IR::U128 operand1 = V(datasize, Vn);
|
|
const IR::U128 operand2 = V(datasize, Vm);
|
|
const IR::U128 result = ir.VectorLogicalVShiftSigned(esize, operand1, operand2);
|
|
V(datasize, Vd, result);
|
|
return true;
|
|
}
|
|
|
|
bool TranslatorVisitor::USHL_2(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
|
|
if (size == 0b11 && !Q) {
|
|
return ReservedValue();
|
|
}
|
|
const size_t esize = 8 << size.ZeroExtend<size_t>();
|
|
const size_t datasize = Q ? 128 : 64;
|
|
|
|
const IR::U128 operand1 = V(datasize, Vn);
|
|
const IR::U128 operand2 = V(datasize, Vm);
|
|
const IR::U128 result = ir.VectorLogicalVShiftUnsigned(esize, operand1, operand2);
|
|
V(datasize, Vd, result);
|
|
return true;
|
|
}
|
|
|
|
bool TranslatorVisitor::UMAX(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
|
|
if (size == 0b11) {
|
|
return ReservedValue();
|
|
}
|
|
const size_t esize = 8 << size.ZeroExtend<size_t>();
|
|
const size_t datasize = Q ? 128 : 64;
|
|
|
|
const IR::U128 operand1 = V(datasize, Vn);
|
|
const IR::U128 operand2 = V(datasize, Vm);
|
|
const IR::U128 result = ir.VectorMaxUnsigned(esize, operand1, operand2);
|
|
V(datasize, Vd, result);
|
|
return true;
|
|
}
|
|
|
|
bool TranslatorVisitor::UABA(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
|
|
if (size == 0b11) {
|
|
return ReservedValue();
|
|
}
|
|
|
|
const size_t datasize = Q ? 128 : 64;
|
|
const size_t esize = 8 << size.ZeroExtend();
|
|
|
|
const IR::U128 operand1 = V(datasize, Vn);
|
|
const IR::U128 operand2 = V(datasize, Vm);
|
|
const IR::U128 initial_dest = V(datasize, Vd);
|
|
|
|
const IR::U128 result = ir.VectorAdd(esize, initial_dest,
|
|
ir.VectorUnsignedAbsoluteDifference(esize, operand1, operand2));
|
|
|
|
V(datasize, Vd, result);
|
|
return true;
|
|
}
|
|
|
|
bool TranslatorVisitor::UABD(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
|
|
if (size == 0b11) {
|
|
return ReservedValue();
|
|
}
|
|
|
|
const size_t datasize = Q ? 128 : 64;
|
|
const size_t esize = 8 << size.ZeroExtend();
|
|
|
|
const IR::U128 operand1 = V(datasize, Vn);
|
|
const IR::U128 operand2 = V(datasize, Vm);
|
|
const IR::U128 result = ir.VectorUnsignedAbsoluteDifference(esize, operand1, operand2);
|
|
|
|
V(datasize, Vd, result);
|
|
return true;
|
|
}
|
|
|
|
bool TranslatorVisitor::UMIN(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
|
|
if (size == 0b11) {
|
|
return ReservedValue();
|
|
}
|
|
const size_t esize = 8 << size.ZeroExtend<size_t>();
|
|
const size_t datasize = Q ? 128 : 64;
|
|
|
|
const IR::U128 operand1 = V(datasize, Vn);
|
|
const IR::U128 operand2 = V(datasize, Vm);
|
|
const IR::U128 result = ir.VectorMinUnsigned(esize, operand1, operand2);
|
|
V(datasize, Vd, result);
|
|
return true;
|
|
}
|
|
|
|
bool TranslatorVisitor::FSUB_2(bool Q, bool sz, Vec Vm, Vec Vn, Vec Vd) {
|
|
if (sz && !Q) {
|
|
return ReservedValue();
|
|
}
|
|
const size_t esize = sz ? 64 : 32;
|
|
const size_t datasize = Q ? 128 : 64;
|
|
|
|
const IR::U128 operand1 = V(datasize, Vn);
|
|
const IR::U128 operand2 = V(datasize, Vm);
|
|
const IR::U128 result = ir.FPVectorSub(esize, operand1, operand2);
|
|
V(datasize, Vd, result);
|
|
return true;
|
|
}
|
|
|
|
bool TranslatorVisitor::ORR_asimd_reg(bool Q, Vec Vm, Vec Vn, Vec Vd) {
|
|
const size_t datasize = Q ? 128 : 64;
|
|
|
|
auto operand1 = V(datasize, Vn);
|
|
auto operand2 = V(datasize, Vm);
|
|
|
|
auto result = ir.VectorOr(operand1, operand2);
|
|
|
|
V(datasize, Vd, result);
|
|
|
|
return true;
|
|
}
|
|
|
|
bool TranslatorVisitor::ORN_asimd(bool Q, Vec Vm, Vec Vn, Vec Vd) {
|
|
const size_t datasize = Q ? 128 : 64;
|
|
|
|
auto operand1 = V(datasize, Vn);
|
|
auto operand2 = V(datasize, Vm);
|
|
|
|
auto result = ir.VectorOr(operand1, ir.VectorNot(operand2));
|
|
|
|
if (datasize == 64) {
|
|
result = ir.VectorZeroUpper(result);
|
|
}
|
|
|
|
V(datasize, Vd, result);
|
|
|
|
return true;
|
|
}
|
|
|
|
bool TranslatorVisitor::SUB_2(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
|
|
if (size == 0b11 && !Q) return ReservedValue();
|
|
const size_t esize = 8 << size.ZeroExtend<size_t>();
|
|
const size_t datasize = Q ? 128 : 64;
|
|
|
|
auto operand1 = V(datasize, Vn);
|
|
auto operand2 = V(datasize, Vm);
|
|
|
|
auto result = ir.VectorSub(esize, operand1, operand2);
|
|
|
|
V(datasize, Vd, result);
|
|
|
|
return true;
|
|
}
|
|
|
|
bool TranslatorVisitor::CMEQ_reg_2(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
|
|
if (size == 0b11 && !Q) return ReservedValue();
|
|
const size_t esize = 8 << size.ZeroExtend<size_t>();
|
|
const size_t datasize = Q ? 128 : 64;
|
|
|
|
const IR::U128 operand1 = V(datasize, Vn);
|
|
const IR::U128 operand2 = V(datasize, Vm);
|
|
|
|
IR::U128 result = ir.VectorEqual(esize, operand1, operand2);
|
|
|
|
if (datasize == 64) {
|
|
result = ir.VectorZeroUpper(result);
|
|
}
|
|
|
|
V(datasize, Vd, result);
|
|
|
|
return true;
|
|
}
|
|
|
|
bool TranslatorVisitor::MLS_vec(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
|
|
if (size == 0b11) return ReservedValue();
|
|
const size_t esize = 8 << size.ZeroExtend<size_t>();
|
|
const size_t datasize = Q ? 128 : 64;
|
|
|
|
const IR::U128 operand1 = V(datasize, Vn);
|
|
const IR::U128 operand2 = V(datasize, Vm);
|
|
const IR::U128 operand3 = V(datasize, Vd);
|
|
|
|
const IR::U128 result = ir.VectorSub(esize, operand3, ir.VectorMultiply(esize, operand1, operand2));
|
|
|
|
V(datasize, Vd, result);
|
|
|
|
return true;
|
|
}
|
|
|
|
bool TranslatorVisitor::EOR_asimd(bool Q, Vec Vm, Vec Vn, Vec Vd) {
|
|
const size_t datasize = Q ? 128 : 64;
|
|
|
|
auto operand1 = V(datasize, Vn);
|
|
auto operand2 = V(datasize, Vm);
|
|
|
|
auto result = ir.VectorEor(operand1, operand2);
|
|
|
|
V(datasize, Vd, result);
|
|
|
|
return true;
|
|
}
|
|
|
|
bool TranslatorVisitor::FADDP_vec_2(bool Q, bool sz, Vec Vm, Vec Vn, Vec Vd) {
|
|
if (sz && !Q) {
|
|
return ReservedValue();
|
|
}
|
|
|
|
const size_t esize = sz ? 64 : 32;
|
|
const size_t datasize = Q ? 128 : 64;
|
|
|
|
const IR::U128 operand1 = V(datasize, Vn);
|
|
const IR::U128 operand2 = V(datasize, Vm);
|
|
const IR::U128 result = Q ? ir.FPVectorPairedAdd(esize, operand1, operand2) : ir.FPVectorPairedAddLower(esize, operand1, operand2);
|
|
V(datasize, Vd, result);
|
|
return true;
|
|
}
|
|
|
|
bool TranslatorVisitor::FMUL_vec_2(bool Q, bool sz, Vec Vm, Vec Vn, Vec Vd) {
|
|
if (sz && !Q) {
|
|
return ReservedValue();
|
|
}
|
|
const size_t esize = sz ? 64 : 32;
|
|
const size_t datasize = Q ? 128 : 64;
|
|
|
|
const IR::U128 operand1 = V(datasize, Vn);
|
|
const IR::U128 operand2 = V(datasize, Vm);
|
|
IR::U128 result = ir.FPVectorMul(esize, operand1, operand2);
|
|
V(datasize, Vd, result);
|
|
return true;
|
|
}
|
|
|
|
bool TranslatorVisitor::FDIV_2(bool Q, bool sz, Vec Vm, Vec Vn, Vec Vd) {
|
|
if (sz && !Q) {
|
|
return ReservedValue();
|
|
}
|
|
const size_t esize = sz ? 64 : 32;
|
|
const size_t datasize = Q ? 128 : 64;
|
|
|
|
const IR::U128 operand1 = V(datasize, Vn);
|
|
const IR::U128 operand2 = V(datasize, Vm);
|
|
IR::U128 result = ir.FPVectorDiv(esize, operand1, operand2);
|
|
if (datasize == 64) {
|
|
result = ir.VectorZeroUpper(result);
|
|
}
|
|
V(datasize, Vd, result);
|
|
return true;
|
|
}
|
|
|
|
bool TranslatorVisitor::BIF(bool Q, Vec Vm, Vec Vn, Vec Vd) {
|
|
const size_t datasize = Q ? 128 : 64;
|
|
|
|
auto operand1 = V(datasize, Vd);
|
|
auto operand4 = V(datasize, Vn);
|
|
auto operand3 = ir.VectorNot(V(datasize, Vm));
|
|
|
|
auto result = ir.VectorEor(operand1, ir.VectorAnd(ir.VectorEor(operand1, operand4), operand3));
|
|
|
|
V(datasize, Vd, result);
|
|
|
|
return true;
|
|
}
|
|
|
|
bool TranslatorVisitor::BIT(bool Q, Vec Vm, Vec Vn, Vec Vd) {
|
|
const size_t datasize = Q ? 128 : 64;
|
|
|
|
auto operand1 = V(datasize, Vd);
|
|
auto operand4 = V(datasize, Vn);
|
|
auto operand3 = V(datasize, Vm);
|
|
|
|
auto result = ir.VectorEor(operand1, ir.VectorAnd(ir.VectorEor(operand1, operand4), operand3));
|
|
|
|
V(datasize, Vd, result);
|
|
|
|
return true;
|
|
}
|
|
|
|
bool TranslatorVisitor::BSL(bool Q, Vec Vm, Vec Vn, Vec Vd) {
|
|
const size_t datasize = Q ? 128 : 64;
|
|
|
|
auto operand4 = V(datasize, Vn);
|
|
auto operand1 = V(datasize, Vm);
|
|
auto operand3 = V(datasize, Vd);
|
|
|
|
auto result = ir.VectorEor(operand1, ir.VectorAnd(ir.VectorEor(operand1, operand4), operand3));
|
|
|
|
V(datasize, Vd, result);
|
|
|
|
return true;
|
|
}
|
|
|
|
} // namespace Dynarmic::A64
|