mirror of
https://github.com/azahar-emu/dynarmic
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e4a733d5b2
git-subtree-dir: externals/biscuit git-subtree-split: 1d53c9e6cfe56544982200a5bac15a5de064936b
225 lines
8.1 KiB
C++
225 lines
8.1 KiB
C++
#pragma once
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#include <biscuit/assert.hpp>
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#include <biscuit/code_buffer.hpp>
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#include <biscuit/registers.hpp>
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#include <cstddef>
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#include <cstdint>
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// Generic internal utility header for various helper functions related
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// to encoding instructions.
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namespace biscuit {
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// Determines if a value lies within the range of a 6-bit immediate.
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[[nodiscard]] constexpr bool IsValidSigned6BitImm(ptrdiff_t value) {
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return value >= -32 && value <= 31;
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}
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// S-type and I-type immediates are 12 bits in size
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[[nodiscard]] constexpr bool IsValidSigned12BitImm(ptrdiff_t value) {
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return value >= -2048 && value <= 2047;
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}
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// B-type immediates only provide -4KiB to +4KiB range branches.
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[[nodiscard]] constexpr bool IsValidBTypeImm(ptrdiff_t value) {
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return value >= -4096 && value <= 4095;
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}
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// J-type immediates only provide -1MiB to +1MiB range branches.
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[[nodiscard]] constexpr bool IsValidJTypeImm(ptrdiff_t value) {
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return value >= -0x80000 && value <= 0x7FFFF;
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}
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// CB-type immediates only provide -256B to +256B range branches.
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[[nodiscard]] constexpr bool IsValidCBTypeImm(ptrdiff_t value) {
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return value >= -256 && value <= 255;
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}
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// CJ-type immediates only provide -2KiB to +2KiB range branches.
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[[nodiscard]] constexpr bool IsValidCJTypeImm(ptrdiff_t value) {
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return IsValidSigned12BitImm(value);
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}
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// Determines whether or not the register fits in 3-bit compressed encoding.
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[[nodiscard]] constexpr bool IsValid3BitCompressedReg(Register reg) {
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const auto index = reg.Index();
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return index >= 8 && index <= 15;
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}
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// Determines whether or not the given shift amount is valid for a compressed shift instruction
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[[nodiscard]] constexpr bool IsValidCompressedShiftAmount(uint32_t shift) {
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return shift > 0 && shift <= 64;
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}
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// Turns a compressed register into its encoding.
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[[nodiscard]] constexpr uint32_t CompressedRegTo3BitEncoding(Register reg) {
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return reg.Index() - 8;
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}
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// Transforms a regular value into an immediate encoded in a B-type instruction.
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[[nodiscard]] constexpr uint32_t TransformToBTypeImm(uint32_t imm) {
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// clang-format off
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return ((imm & 0x07E0) << 20) |
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((imm & 0x1000) << 19) |
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((imm & 0x001E) << 7) |
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((imm & 0x0800) >> 4);
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// clang-format on
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}
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// Transforms a regular value into an immediate encoded in a J-type instruction.
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[[nodiscard]] constexpr uint32_t TransformToJTypeImm(uint32_t imm) {
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// clang-format off
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return ((imm & 0x0FF000) >> 0) |
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((imm & 0x000800) << 9) |
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((imm & 0x0007FE) << 20) |
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((imm & 0x100000) << 11);
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// clang-format on
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}
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// Transforms a regular value into an immediate encoded in a CB-type instruction.
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[[nodiscard]] constexpr uint32_t TransformToCBTypeImm(uint32_t imm) {
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// clang-format off
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return ((imm & 0x0C0) >> 1) |
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((imm & 0x006) << 2) |
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((imm & 0x020) >> 3) |
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((imm & 0x018) << 7) |
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((imm & 0x100) << 4);
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// clang-format on
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}
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// Transforms a regular value into an immediate encoded in a CJ-type instruction.
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[[nodiscard]] constexpr uint32_t TransformToCJTypeImm(uint32_t imm) {
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// clang-format off
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return ((imm & 0x800) << 1) |
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((imm & 0x010) << 7) |
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((imm & 0x300) << 1) |
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((imm & 0x400) >> 2) |
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((imm & 0x040) << 1) |
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((imm & 0x080) >> 1) |
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((imm & 0x00E) << 4) |
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((imm & 0x020) >> 3);
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// clang-format on
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}
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// Emits a B type RISC-V instruction. These consist of:
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// imm[12|10:5] | rs2 | rs1 | funct3 | imm[4:1] | imm[11] | opcode
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inline void EmitBType(CodeBuffer& buffer, uint32_t imm, GPR rs2, GPR rs1,
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uint32_t funct3, uint32_t opcode) {
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imm &= 0x1FFE;
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buffer.Emit32(TransformToBTypeImm(imm) | (rs2.Index() << 20) | (rs1.Index() << 15) |
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((funct3 & 0b111) << 12) | (opcode & 0x7F));
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}
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// Emits a I type RISC-V instruction. These consist of:
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// imm[11:0] | rs1 | funct3 | rd | opcode
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inline void EmitIType(CodeBuffer& buffer, uint32_t imm, Register rs1, uint32_t funct3,
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Register rd, uint32_t opcode) {
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imm &= 0xFFF;
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buffer.Emit32((imm << 20) | (rs1.Index() << 15) | ((funct3 & 0b111) << 12) |
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(rd.Index() << 7) | (opcode & 0x7F));
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}
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// Emits a J type RISC-V instruction. These consist of:
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// imm[20|10:1|11|19:12] | rd | opcode
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inline void EmitJType(CodeBuffer& buffer, uint32_t imm, GPR rd, uint32_t opcode) {
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imm &= 0x1FFFFE;
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buffer.Emit32(TransformToJTypeImm(imm) | rd.Index() << 7 | (opcode & 0x7F));
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}
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// Emits a R type RISC instruction. These consist of:
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// funct7 | rs2 | rs1 | funct3 | rd | opcode
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inline void EmitRType(CodeBuffer& buffer, uint32_t funct7, Register rs2, Register rs1,
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uint32_t funct3, Register rd, uint32_t opcode) {
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// clang-format off
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const auto value = ((funct7 & 0xFF) << 25) |
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(rs2.Index() << 20) |
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(rs1.Index() << 15) |
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((funct3 & 0b111) << 12) |
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(rd.Index() << 7) |
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(opcode & 0x7F);
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// clang-format off
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buffer.Emit32(value);
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}
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// Emits a R type RISC instruction. These consist of:
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// funct7 | rs2 | rs1 | funct3 | rd | opcode
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inline void EmitRType(CodeBuffer& buffer, uint32_t funct7, FPR rs2, FPR rs1, RMode funct3,
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FPR rd, uint32_t opcode) {
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EmitRType(buffer, funct7, rs2, rs1, static_cast<uint32_t>(funct3), rd, opcode);
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}
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// Emits a R4 type RISC instruction. These consist of:
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// rs3 | funct2 | rs2 | rs1 | funct3 | rd | opcode
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inline void EmitR4Type(CodeBuffer& buffer, FPR rs3, uint32_t funct2, FPR rs2, FPR rs1,
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RMode funct3, FPR rd, uint32_t opcode) {
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const auto reg_bits = (rs3.Index() << 27) | (rs2.Index() << 20) | (rs1.Index() << 15) | (rd.Index() << 7);
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const auto funct_bits = ((funct2 & 0b11) << 25) | (static_cast<uint32_t>(funct3) << 12);
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buffer.Emit32(reg_bits | funct_bits | (opcode & 0x7F));
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}
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// Emits a S type RISC-V instruction. These consist of:
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// imm[11:5] | rs2 | rs1 | funct3 | imm[4:0] | opcode
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inline void EmitSType(CodeBuffer& buffer, uint32_t imm, Register rs2, GPR rs1,
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uint32_t funct3, uint32_t opcode) {
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imm &= 0xFFF;
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// clang-format off
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const auto new_imm = ((imm & 0x01F) << 7) |
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((imm & 0xFE0) << 20);
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// clang-format on
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buffer.Emit32(new_imm | (rs2.Index() << 20) | (rs1.Index() << 15) |
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((funct3 & 0b111) << 12) | (opcode & 0x7F));
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}
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// Emits a U type RISC-V instruction. These consist of:
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// imm[31:12] | rd | opcode
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inline void EmitUType(CodeBuffer& buffer, uint32_t imm, GPR rd, uint32_t opcode) {
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buffer.Emit32((imm & 0x000FFFFF) << 12 | rd.Index() << 7 | (opcode & 0x7F));
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}
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// Emits an atomic instruction.
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inline void EmitAtomic(CodeBuffer& buffer, uint32_t funct5, Ordering ordering, GPR rs2, GPR rs1,
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uint32_t funct3, GPR rd, uint32_t opcode) noexcept {
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const auto funct7 = (funct5 << 2) | static_cast<uint32_t>(ordering);
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EmitRType(buffer, funct7, rs2, rs1, funct3, rd, opcode);
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}
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// Emits a fence instruction
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inline void EmitFENCE(CodeBuffer& buffer, uint32_t fm, FenceOrder pred, FenceOrder succ,
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GPR rs, uint32_t funct3, GPR rd, uint32_t opcode) noexcept {
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// clang-format off
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buffer.Emit32(((fm & 0b1111) << 28) |
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(static_cast<uint32_t>(pred) << 24) |
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(static_cast<uint32_t>(succ) << 20) |
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(rs.Index() << 15) |
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((funct3 & 0b111) << 12) |
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(rd.Index() << 7) |
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(opcode & 0x7F));
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// clang-format on
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}
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// Internal helpers for siloing away particular comparisons for behavior.
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constexpr bool IsRV32(ArchFeature feature) {
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return feature == ArchFeature::RV32;
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}
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constexpr bool IsRV64(ArchFeature feature) {
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return feature == ArchFeature::RV64;
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}
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constexpr bool IsRV128(ArchFeature feature) {
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return feature == ArchFeature::RV128;
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}
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constexpr bool IsRV32OrRV64(ArchFeature feature) {
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return IsRV32(feature) || IsRV64(feature);
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}
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constexpr bool IsRV64OrRV128(ArchFeature feature) {
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return IsRV64(feature) || IsRV128(feature);
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}
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} // namespace biscuit
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