mirror of
https://github.com/azahar-emu/dynarmic
synced 2025-11-07 15:40:00 +01:00
108 lines
4.1 KiB
C++
108 lines
4.1 KiB
C++
/* This file is part of the dynarmic project.
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* Copyright (c) 2020 MerryMage
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* SPDX-License-Identifier: 0BSD
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*/
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#include "common/bit_util.h"
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#include "frontend/A32/translate/impl/translate_arm.h"
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namespace Dynarmic::A32 {
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namespace {
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ExtReg ToExtReg(size_t base, bool bit) {
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return ExtReg::D0 + (base + (bit ? 16 : 0));
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}
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template <typename Callable>
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bool BitwiseInstruction(ArmTranslatorVisitor& v, bool D, size_t Vn, size_t Vd, bool N, bool Q, bool M, size_t Vm, Callable fn) {
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if (Q && (Common::Bit<0>(Vd) || Common::Bit<0>(Vn) || Common::Bit<0>(Vm))) {
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return v.UndefinedInstruction();
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}
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const auto d = ToExtReg(Vd, D);
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const auto m = ToExtReg(Vm, M);
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const auto n = ToExtReg(Vn, N);
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const size_t regs = Q ? 2 : 1;
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for (size_t i = 0; i < regs; i++) {
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const IR::U32U64 reg_m = v.ir.GetExtendedRegister(m + i);
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const IR::U32U64 reg_n = v.ir.GetExtendedRegister(n + i);
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const IR::U32U64 result = fn(reg_n, reg_m);
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v.ir.SetExtendedRegister(d + i, result);
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}
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return true;
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}
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template <typename Callable>
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bool BitwiseInstructionWithDst(ArmTranslatorVisitor& v, bool D, size_t Vn, size_t Vd, bool N, bool Q, bool M, size_t Vm, Callable fn) {
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if (Q && (Common::Bit<0>(Vd) || Common::Bit<0>(Vn) || Common::Bit<0>(Vm))) {
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return v.UndefinedInstruction();
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}
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const auto d = ToExtReg(Vd, D);
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const auto m = ToExtReg(Vm, M);
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const auto n = ToExtReg(Vn, N);
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const size_t regs = Q ? 2 : 1;
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for (size_t i = 0; i < regs; i++) {
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const IR::U32U64 reg_d = v.ir.GetExtendedRegister(d + i);
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const IR::U32U64 reg_m = v.ir.GetExtendedRegister(m + i);
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const IR::U32U64 reg_n = v.ir.GetExtendedRegister(n + i);
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const IR::U32U64 result = fn(reg_d, reg_n, reg_m);
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v.ir.SetExtendedRegister(d + i, result);
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}
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return true;
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}
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} // Anonymous namespace
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bool ArmTranslatorVisitor::asimd_VAND_reg(bool D, size_t Vn, size_t Vd, bool N, bool Q, bool M, size_t Vm) {
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return BitwiseInstruction(*this, D, Vn, Vd, N, Q, M, Vm, [this](const auto& reg_n, const auto& reg_m) {
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return ir.And(reg_n, reg_m);
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});
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}
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bool ArmTranslatorVisitor::asimd_VBIC_reg(bool D, size_t Vn, size_t Vd, bool N, bool Q, bool M, size_t Vm) {
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return BitwiseInstruction(*this, D, Vn, Vd, N, Q, M, Vm, [this](const auto& reg_n, const auto& reg_m) {
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return ir.And(reg_n, ir.Not(reg_m));
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});
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}
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bool ArmTranslatorVisitor::asimd_VORR_reg(bool D, size_t Vn, size_t Vd, bool N, bool Q, bool M, size_t Vm) {
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return BitwiseInstruction(*this, D, Vn, Vd, N, Q, M, Vm, [this](const auto& reg_n, const auto& reg_m) {
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return ir.Or(reg_n, reg_m);
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});
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}
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bool ArmTranslatorVisitor::asimd_VORN_reg(bool D, size_t Vn, size_t Vd, bool N, bool Q, bool M, size_t Vm) {
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return BitwiseInstruction(*this, D, Vn, Vd, N, Q, M, Vm, [this](const auto& reg_n, const auto& reg_m) {
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return ir.Or(reg_n, ir.Not(reg_m));
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});
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}
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bool ArmTranslatorVisitor::asimd_VEOR_reg(bool D, size_t Vn, size_t Vd, bool N, bool Q, bool M, size_t Vm) {
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return BitwiseInstruction(*this, D, Vn, Vd, N, Q, M, Vm, [this](const auto& reg_n, const auto& reg_m) {
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return ir.Eor(reg_n, reg_m);
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});
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}
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bool ArmTranslatorVisitor::asimd_VBSL(bool D, size_t Vn, size_t Vd, bool N, bool Q, bool M, size_t Vm) {
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return BitwiseInstructionWithDst(*this, D, Vn, Vd, N, Q, M, Vm, [this](const auto& reg_d, const auto& reg_n, const auto& reg_m) {
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return ir.Or(ir.And(reg_n, reg_d), ir.And(reg_m, ir.Not(reg_d)));
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});
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}
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bool ArmTranslatorVisitor::asimd_VBIT(bool D, size_t Vn, size_t Vd, bool N, bool Q, bool M, size_t Vm) {
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return BitwiseInstructionWithDst(*this, D, Vn, Vd, N, Q, M, Vm, [this](const auto& reg_d, const auto& reg_n, const auto& reg_m) {
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return ir.Or(ir.And(reg_n, reg_m), ir.And(reg_d, ir.Not(reg_m)));
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});
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}
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bool ArmTranslatorVisitor::asimd_VBIF(bool D, size_t Vn, size_t Vd, bool N, bool Q, bool M, size_t Vm) {
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return BitwiseInstructionWithDst(*this, D, Vn, Vd, N, Q, M, Vm, [this](const auto& reg_d, const auto& reg_n, const auto& reg_m) {
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return ir.Or(ir.And(reg_d, reg_m), ir.And(reg_n, ir.Not(reg_m)));
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});
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}
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} // namespace Dynarmic::A32
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