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Commit Graph

322 Commits

Author SHA1 Message Date
MerryMage
faeb77e8c4 A64: Implement SUB (vector) 2020-04-22 20:46:14 +01:00
MerryMage
bd106c3ae7 A64: Implement SIMD instruction SSRA, vector variant 2020-04-22 20:46:14 +01:00
MerryMage
f58aba9871 A64: Implement SIMD instruction SSHR, vector variant 2020-04-22 20:46:14 +01:00
MerryMage
e858ce0b35 A64: Implement SIMD instructions XTN, XTN2 2020-04-22 20:46:13 +01:00
MerryMage
3f93c77ace A64: Implement SIMD instruction USRA, vector variant 2020-04-22 20:46:13 +01:00
MerryMage
fb9d20f27f A64: Implement SIMD instruction USHR, vector variant 2020-04-22 20:46:13 +01:00
MerryMage
7ff280827b A64: Implement SIMD instructions USHLL, USHLL2 2020-04-22 20:46:13 +01:00
MerryMage
1d0cd95b23 A64: Implement SIMD instruction SHL 2020-04-22 20:46:13 +01:00
FernandoS27
15871910af Implemented BSL, BIC, BIT and BIF vector instructions 2020-04-22 20:46:13 +01:00
Lioncash
35a29a9665 A64: Implement ZIP1 2020-04-22 20:46:13 +01:00
FernandoS27
586854117b Implemented UMULH and SMULH instructions 2020-04-22 20:46:13 +01:00
MerryMage
1a7b7b541a A64: Implement MOVI, MVNI, ORR (vector, immediate), BIC (vector, immediate) 
There wasn't a clean way to seperate these instructions out.
 2020-04-22 20:46:13 +01:00
MerryMage
ea69cb4474 A64: Implement SUB (vector), scalar variant 2020-04-22 20:46:13 +01:00
MerryMage
4c5871d5d5 A64: Implement ADD (vector), scalar variant 2020-04-22 20:46:13 +01:00
MerryMage
2a0850c068 A64: Reorganize decoder tables (some vector entries were grouped with scalar entries) 2020-04-22 20:46:13 +01:00
MerryMage
7b33772ac6 A64: Implement BIC (vector, register) 2020-04-22 20:46:13 +01:00
MerryMage
eb5591859c A64: Implement FMOV (general) 2020-04-22 20:46:13 +01:00
MerryMage
cc9efd13c9 A64: Implement STLLRB, STLLRH, STLLR, LDLARB, LDLARH, LDLAR 2020-04-22 20:46:13 +01:00
MerryMage
81713c2b77 A64: Implement FCCMPE 2020-04-22 20:46:13 +01:00
MerryMage
ef906dbbfa A64: Implement FCCMP 2020-04-22 20:46:13 +01:00
Lioncash
2ee39d6b36 A64: Implement FMOV (register) 2020-04-22 20:46:13 +01:00
MerryMage
b02b861242 A64: Implement STLRB, STLRH, STLR, LDARB, LDARH, LDAR 2020-04-22 20:46:13 +01:00
Lioncash
5a65313236 A64: Implement CCMP (immediate) 2020-04-22 20:46:13 +01:00
Lioncash
ab4664de61 A64: Implement CCMN (immediate) 2020-04-22 20:46:13 +01:00
Lioncash
a6c6539109 A64: Implement CCMP (register) 2020-04-22 20:46:13 +01:00
MerryMage
c5033b5dda A64: Implement CCMN (register) 2020-04-22 20:46:13 +01:00
MerryMage
4491746eae A64: Implement FNEG 2020-04-22 20:46:13 +01:00
MerryMage
db958061a3 A64: Implement FABS 2020-04-22 20:46:13 +01:00
MerryMage
8765b421b7 A64: Implement FCSEL 2020-04-22 20:46:13 +01:00
MerryMage
7e82d8eede A64: Implement SCVTF (scalar, integer), UCVTF (scalar, integer) 2020-04-22 20:46:13 +01:00
MerryMage
2409e5d082 A64: Implement FCVTZS (scalar, integer), FCVTZU (scalar, integer) 2020-04-22 20:46:13 +01:00
MerryMage
56bc7825ef A64: Implement STR{,B,H} (register), LDR{,B,H,SB,SH,SW} (register), PFRM (register) 2020-04-22 20:46:13 +01:00
Lioncash
40614202e7 A64: Implement AESD 2020-04-22 20:46:13 +01:00
Lioncash
ccef85dbb7 A64: Implement AESE 2020-04-22 20:46:13 +01:00
MerryMage
0bb4474fb9 A64: Implement INS (general) 2020-04-22 20:46:13 +01:00
MerryMage
d13704fdef A64: Implement INS (element) 2020-04-22 20:46:13 +01:00
MerryMage
0642d49919 A64: Implement SMOV 2020-04-22 20:46:13 +01:00
MerryMage
5297027ebe A64: Implement UMOV 2020-04-22 20:46:13 +01:00
MerryMage
1fb0957aa3 A64: Implement FCVT 2020-04-22 20:46:13 +01:00
MerryMage
4be55b8b84 A64: Implement FMOV (scalar, immediate) 2020-04-22 20:46:13 +01:00
MerryMage
a07c05ea51 A64: Implement STUR (SIMD&FP), LDUR (SIMD&FP) 2020-04-22 20:46:13 +01:00
MerryMage
93fcbdf1e2 A64: Implement FCMP, FCMPE 2020-04-22 20:46:13 +01:00
MerryMage
99d8ebe4d5 A64: Implement FMUL (scalar), FDIV (scalar), FADD (scalar), FSUB (scalar), FNMUL (scalar) 2020-04-22 20:46:13 +01:00
MerryMage
ed2bedec43 A64: Implement {ST,LD}{1,2,3,4} (multiple structures) 2020-04-22 20:46:13 +01:00
Lioncash
a5c4fbc783 A64: Implement AESIMC and AESMC 2020-04-22 20:46:13 +01:00
Lioncash
af1384d700 A64: Implement CRC32 2020-04-22 20:46:12 +01:00
Lioncash
7ffbebf290 A64: Implement CRC32C 2020-04-22 20:46:12 +01:00
Lioncash
7734cf1050 A64: Implement EXTR 2020-04-22 20:46:12 +01:00
MerryMage
88ae7fce52 A64: Implement LDP (SIMD&FP) and STP (SIMD&FP) 2020-04-22 20:44:38 +01:00
MerryMage
75756137c6 A64: Implement CMEQ (register, vector) 2020-04-22 20:44:38 +01:00