5 Commits

Author	SHA1	Message	Date
Lioncash	841098a0bc	ir: separate components out a little more	2016-08-17 20:46:21 +01:00
MerryMage	e164ede4dc	TranslateArm: Implement MRS, MSR (imm), MSR (reg)	2016-08-15 11:50:49 +01:00
MerryMage	be87038ffd	IROpt: Port get/set elimination pass to current IR	2016-08-02 11:51:05 +01:00
MerryMage	51448aa06d	More Speed	2016-07-22 23:55:00 +01:00
MerryMage	5fbfc6c155	Implement some simple IR optimizations (get/set eliminiation and DCE)	2016-07-21 21:48:45 +01:00